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Looks like Intel has added two more USB 2.0 ports from LynxPoint to
Broadwell, which shifted the port offsets of the USB 3.0 ports behind
them. The USB 2.0 ports are now 0x480 to 0x520 and the 3.0 ones 0x530 to
0x560 (at least according to what my kernel seems to think). The offset
of the first USB 3.0 port is hardcoded and seems to have been copied
over without accounting for this, meaning when we try to operate on all
USB 3.0 ports we actually operate on the last two 2.0 and the first two
3.0 ports instead.
This patch should fix the bug for now. In the future, we might want to
consider dynamically detecting port locations through the Protocol
Capability structures at the end of the XHCI register set instead.
BRANCH=samus
BUG=chrome-os-partner:35320
TEST=TODO
Change-Id: Ifab6e484980fd4cd0daf80ceb292ddced2ab1aea
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 525f359c0b6b95b260add2b4617fd86119d69397
Original-Change-Id: Ic2becf2b043612270909ceef66e7d58efc8fcbe1
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/247351
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: http://review.coreboot.org/9502
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This function will use the next available/free protected range
register to cover the specified region of flash and write
protect it until the next reset.
This will be used by the common MRC cache code to protect the
RW_MRC_CACHE region after it is updated.
In order to communicate to the common NVM code that this function
is defined also enable CONFIG_MRC_SETTINGS_PROTECT variable.
BUG=chrome-os-partner:28234
BRANCH=broadwell
TEST=build and boot on samus
Change-Id: I710c6a69f725479411ed978cc615e1bb78fb42b8
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 25365433be0f190e10a96d9946b8ea90c883b78a
Original-Change-Id: I4a4cd27f9f4a94b9134dcba623f33b114299818f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241129
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9493
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The registers that were used here are for CPT/PPT and not
for HSW/BDW chips.
Update this to update just the Gen3 TX Output Voltage Downscale
Amplitude Adjustment field in the SATA ECR T88.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: I94b702dc4a3c98678ba048ff9cfa4a85cc5b1eed
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4c5816cc647b84266751e8a591eb85d7735fee12
Original-Change-Id: I98ec9678938a6675828721d5b57683077f555d21
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238800
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9484
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In order to report the GPE that woke the system to the kernel
coreboot needs to keep track of the first GPE wake source and
save it in NVS so it can be returned in \_GPE._SWS method.
This is similar to the saving of PM1 status but needs to go
through all the GPE0_STS registers and check for enabled and
triggered events.
A bit of cleanup is done for areas that were touched:
- platform.asl was not formatted correctly
BUG=chrome-os-partner:8127
BRANCH=samus,auron
TEST=manual:
- suspend/resume and wake from EC event like keyboard:
ACPI _SWS is PM1 Index -1 GPE Index 112 ("special" GPIO27)
- suspend/resume and wake from RTC event:
ACPI _SWS is PM1 Index 10 GPE Index -1 (RTC)
- suspend/resume and wake from power button:
ACPI _SWS is PM1 Index 8 GPE Index -1
- suspend/resume and wake from touchpad:
ACPI _SWS is PM1 Index -1 GPE Index 13
- suspend/resume and wake from WLAN:
ACPI _SWS is PM1 Index -1 GPE Index 10
Change-Id: I574f8cd83c8bb42f420e1a00e71a23aa23195f53
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: d4e06c7dfc73f2952ce8f81263e316980aa9760f
Original-Change-Id: I9bfbbe4385f2acc2a50f41ae321b4bae262b7078
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220324
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9460
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch aligns broadwell to the new SoC header include scheme.
BUG=None
TEST=Tested with whole series. Compiled Auron and Samus.
Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e
Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224507
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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