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path: root/src/soc/intel/broadwell/include
AgeCommit message (Expand)Author
2018-12-20soc/intel/broadwell: implement RMRR ACPI tableMatt DeVillier
2018-12-05soc/intel/broadwell: Implement postcar stageArthur Heymans
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-10-22intel: Use CF9 reset (part 1)Patrick Rudolph
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
2018-10-08Move compiler.h to commonlibNico Huber
2018-10-05src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS
2018-09-21soc/broadwell: Don't use device_tElyes HAOUAS
2018-09-17soc/intel/broadwell: Add PCH_GPIO_PIRQ_INVERT definitionMatt DeVillier
2018-08-22cbtable: remove chromeos_acpi from cbtableJoel Kitching
2018-06-01soc/intel/broadwell: Get rid of device_tElyes HAOUAS
2018-05-31soc/intel/broadwell: decouple PEI memory struct from coreboot headerMatt DeVillier
2018-04-26src: Fix a typo on "mtrr"Elyes HAOUAS
2018-03-15soc/intel/broadwell: add support for Intel GMA OpRegionMatt DeVillier
2018-03-01soc/intel/broadwell: Generate ACPI DMAR tableMatt DeVillier
2018-03-01soc/intel/broadwell: Enable VT-d and X2APICMatt DeVillier
2017-12-16soc/intel/broadwell: implement spi_flash_ctrlr_protect_region()Aaron Durbin
2017-11-04sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer
2017-09-20soc/intel/broadwell: refactor rtc failure checkingAaron Durbin
2017-07-13soc/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
2017-06-07src: change coreboot to lowercaseMartin Roth
2017-03-17soc/intel/broadwell: Fix other issues detected by checkpatchLee Leahy
2017-03-17soc/intel/broadwell: Fix {}, () and conditional issuesLee Leahy
2017-03-17soc/intel/broadwell: Add int to unsignedLee Leahy
2017-03-17soc/intel/broadwell: Fix spacing issues detected by checkpatchLee Leahy
2017-03-10soc/intel/broadwell: Rework IGD's CDClk selectionNico Huber
2017-02-22Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.Youness Alaoui
2016-12-07soc/broadwell: set EM4/EM5 registers based on cdclkMatt DeVillier
2016-07-30chromeos mainboards: remove chromeos.aslAaron Durbin
2016-07-15soc/intel/broadwell: use common Intel ACPI hardware definitionsAaron Durbin
2016-05-06soc/intel/broadwell: convert to using common MP and SMM initAaron Durbin
2015-12-27broadwell: Fix SATA Gen3 DTLE configuration registersDuncan Laurie
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-09-22coreboot: introduce commonlibAaron Durbin
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-04-18broadwell: Set C9/C10 vccminDuncan Laurie
2015-04-18broadwell: add ROM stage pre console init call backWenkai Du
2015-04-15broadwell: Fixes for _SWS supportDuncan Laurie
2015-04-15broadwell: Clean up ME device and add new ME10 flowDuncan Laurie
2015-04-14broadwell: Remove TPM device from lpc.aslDuncan Laurie
2015-04-10broadwell: Correct XHCI offset for USB 3.0 portsJulius Werner
2015-04-10broadwell: Add function to apply PRR to a range of SPI flashDuncan Laurie
2015-04-10broadwell: Update SATA Gen3 TX adjustment registersDuncan Laurie
2015-04-10broadwell: Add support for ACPI \_GPE._SWSDuncan Laurie
2015-04-07broadwell: Change all SoC headers to <soc/headername.h> systemJulius Werner