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Age
Commit message (
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Author
2018-12-20
soc/intel/broadwell: implement RMRR ACPI table
Matt DeVillier
2018-12-05
soc/intel/broadwell: Implement postcar stage
Arthur Heymans
2018-11-12
src: Remove unneeded include "{arch,cpu}/cpu.h"
Elyes HAOUAS
2018-10-22
intel: Use CF9 reset (part 1)
Patrick Rudolph
2018-10-11
src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Elyes HAOUAS
2018-10-08
Move compiler.h to commonlib
Nico Huber
2018-10-05
src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
Elyes HAOUAS
2018-09-21
soc/broadwell: Don't use device_t
Elyes HAOUAS
2018-09-17
soc/intel/broadwell: Add PCH_GPIO_PIRQ_INVERT definition
Matt DeVillier
2018-08-22
cbtable: remove chromeos_acpi from cbtable
Joel Kitching
2018-06-01
soc/intel/broadwell: Get rid of device_t
Elyes HAOUAS
2018-05-31
soc/intel/broadwell: decouple PEI memory struct from coreboot header
Matt DeVillier
2018-04-26
src: Fix a typo on "mtrr"
Elyes HAOUAS
2018-03-15
soc/intel/broadwell: add support for Intel GMA OpRegion
Matt DeVillier
2018-03-01
soc/intel/broadwell: Generate ACPI DMAR table
Matt DeVillier
2018-03-01
soc/intel/broadwell: Enable VT-d and X2APIC
Matt DeVillier
2017-12-16
soc/intel/broadwell: implement spi_flash_ctrlr_protect_region()
Aaron Durbin
2017-11-04
sb and soc: Enforce correct offset of member "chromeos" in global_nvs_t
Jonathan Neuschäfer
2017-09-20
soc/intel/broadwell: refactor rtc failure checking
Aaron Durbin
2017-07-13
soc/intel: add IS_ENABLED() around Kconfig symbol references
Martin Roth
2017-07-13
Rename __attribute__((packed)) --> __packed
Stefan Reinauer
2017-06-07
src: change coreboot to lowercase
Martin Roth
2017-03-17
soc/intel/broadwell: Fix other issues detected by checkpatch
Lee Leahy
2017-03-17
soc/intel/broadwell: Fix {}, () and conditional issues
Lee Leahy
2017-03-17
soc/intel/broadwell: Add int to unsigned
Lee Leahy
2017-03-17
soc/intel/broadwell: Fix spacing issues detected by checkpatch
Lee Leahy
2017-03-10
soc/intel/broadwell: Rework IGD's CDClk selection
Nico Huber
2017-02-22
Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.
Youness Alaoui
2016-12-07
soc/broadwell: set EM4/EM5 registers based on cdclk
Matt DeVillier
2016-07-30
chromeos mainboards: remove chromeos.asl
Aaron Durbin
2016-07-15
soc/intel/broadwell: use common Intel ACPI hardware definitions
Aaron Durbin
2016-05-06
soc/intel/broadwell: convert to using common MP and SMM init
Aaron Durbin
2015-12-27
broadwell: Fix SATA Gen3 DTLE configuration registers
Duncan Laurie
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-15
cpu/mtrr.h: Fix macro names for MTRR registers
Alexandru Gagniuc
2015-09-22
coreboot: introduce commonlib
Aaron Durbin
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-04-18
broadwell: Set C9/C10 vccmin
Duncan Laurie
2015-04-18
broadwell: add ROM stage pre console init call back
Wenkai Du
2015-04-15
broadwell: Fixes for _SWS support
Duncan Laurie
2015-04-15
broadwell: Clean up ME device and add new ME10 flow
Duncan Laurie
2015-04-14
broadwell: Remove TPM device from lpc.asl
Duncan Laurie
2015-04-10
broadwell: Correct XHCI offset for USB 3.0 ports
Julius Werner
2015-04-10
broadwell: Add function to apply PRR to a range of SPI flash
Duncan Laurie
2015-04-10
broadwell: Update SATA Gen3 TX adjustment registers
Duncan Laurie
2015-04-10
broadwell: Add support for ACPI \_GPE._SWS
Duncan Laurie
2015-04-07
broadwell: Change all SoC headers to <soc/headername.h> system
Julius Werner