| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-11-10 | soc/intel/broadwell: Don't reinitialize SPI after lockdown | Arthur Heymans |
| 2019-07-21 | soc/intel: Expand SA_DEV_ROOT for ramstage | Kyösti Mälkki |
| 2019-03-08 | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner |
| 2015-12-27 | broadwell: Fix CONFIG_SPI_CONSOLE usage | Duncan Laurie |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-04-15 | broadwell: Clean up ME device and add new ME10 flow | Duncan Laurie |
| 2015-04-10 | broadwell: Add a few bits to finalize step | Duncan Laurie |
| 2015-04-07 | broadwell: Change all SoC headers to <soc/headername.h> system | Julius Werner |
| 2015-03-27 | broadwell: fixed power gating enable for disabled sata port | Kane Chen |
| 2015-03-18 | bootstate: use structure pointers for scheduling callbacks | Aaron Durbin |
| 2014-10-22 | broadwell: add new intel SOC | Duncan Laurie |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |