Age | Commit message (Expand) | Author |
2018-11-05 | src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage | Frans Hendriks |
2018-10-23 | src: Remove unneeded whitespace | Elyes HAOUAS |
2018-10-08 | Move compiler.h to commonlib | Nico Huber |
2018-06-04 | soc/intel/braswell: Get rid of device_t | Elyes HAOUAS |
2018-04-24 | compiler.h: add __weak macro | Aaron Durbin |
2017-09-20 | soc/intel/braswell: refactor rtc failure checking | Aaron Durbin |
2017-08-25 | soc/intel/braswell: Put SERIRQ in quiet mode | Hannah Williams |
2017-08-07 | soc/intel/braswell: Fix SPI write after FLOCKDN is set | Hannah Williams |
2017-03-17 | soc/intel/braswell: Fix most of the issues detected by checkpatch | Lee Leahy |
2017-03-17 | soc/intel/braswell: Add int to unsigned | Lee Leahy |
2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
2015-07-06 | Braswell: Update the ACPI tables | Lee Leahy |
2015-06-25 | Braswell: Add Braswell SOC support | Lee Leahy |
2015-05-28 | Remove address from GPLv2 headers | Patrick Georgi |
2015-05-23 | Braswell: Use Baytrail as Comparison Base | Lee Leahy |