summaryrefslogtreecommitdiff
path: root/src/soc/intel/braswell/southcluster.c
AgeCommit message (Expand)Author
2018-11-16src: Remove unneeded include <cbmem.h>Elyes HAOUAS
2018-11-05src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstageFrans Hendriks
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
2018-10-08Move compiler.h to commonlibNico Huber
2018-06-04soc/intel/braswell: Get rid of device_tElyes HAOUAS
2018-04-24compiler.h: add __weak macroAaron Durbin
2017-09-20soc/intel/braswell: refactor rtc failure checkingAaron Durbin
2017-08-25soc/intel/braswell: Put SERIRQ in quiet modeHannah Williams
2017-08-07soc/intel/braswell: Fix SPI write after FLOCKDN is setHannah Williams
2017-03-17soc/intel/braswell: Fix most of the issues detected by checkpatchLee Leahy
2017-03-17soc/intel/braswell: Add int to unsignedLee Leahy
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-07-06Braswell: Update the ACPI tablesLee Leahy
2015-06-25Braswell: Add Braswell SOC supportLee Leahy
2015-05-28Remove address from GPLv2 headersPatrick Georgi
2015-05-23Braswell: Use Baytrail as Comparison BaseLee Leahy
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 08:00:31 +0000