| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-10-11 | intel fsp1_1: prepare for romstage vboot verification split | Aaron Durbin |
| 2015-10-11 | soc/intel/common: remove chipset specific calls | Aaron Durbin |
| 2015-10-11 | intel SOC common: Remove unused parameters | Lee Leahy |
| 2015-09-10 | fsp1_1: provide binding to UEFI version | Aaron Durbin |
| 2015-08-29 | fsp raminit: Add romstage_params to soc_memory_init_params | Duncan Laurie |
| 2015-07-06 | Braswell: Update to end of June. | Lee Leahy |
| 2015-06-25 | Braswell: Add Braswell SOC support | Lee Leahy |
| 2015-06-09 | stage_cache: use cbmem init hooks | Aaron Durbin |
| 2015-06-08 | Remove empty lines at end of file | Elyes HAOUAS |
| 2015-06-02 | cbfs: new API and better program loading | Aaron Durbin |
| 2015-05-28 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-05-27 | Move TPM code out of chromeos | Vladimir Serbinenko |
| 2015-05-23 | Braswell: Use Baytrail as Comparison Base | Lee Leahy |
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index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |