| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-08-14 | intel/common: fix stage_cache_external_region() | Aaron Durbin |
| 2015-07-21 | intel fsp: remove CHIPSET_RESERVED_MEM_BYTES | Aaron Durbin |
| 2015-06-25 | Braswell: Add Braswell SOC support | Lee Leahy |
| 2015-05-28 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-05-23 | Braswell: Use Baytrail as Comparison Base | Lee Leahy |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |