| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-04-04 | soc/intel/braswell: Correct serial IRQ support | Frans Hendriks |
| 2018-09-21 | soc/intel/braswell/ramstage.c: Add SoC stepping D-1 support | Frans Hendriks |
| 2017-08-25 | soc/intel/braswell: Put SERIRQ in quiet mode | Hannah Williams |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-06-25 | Braswell: Add Braswell SOC support | Lee Leahy |
| 2015-05-28 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-05-23 | Braswell: Use Baytrail as Comparison Base | Lee Leahy |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |