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Author
2016-01-28
Braswell: Separate L1 Sub State init procedure for boards.
Kenji Chen
2016-01-07
intel/braswell: Disable IFD & ME by default so abuild can build
Martin Roth
2015-10-27
FSP1_1: Always use common code
Lee Leahy
2015-10-27
FSP 1.1: Move common FSP code
Lee Leahy
2015-10-05
Add EM100 'hyper term' spi console support in ramstage & smm
Martin Roth
2015-09-17
braswell: Switch to using common ACPI _SWS code
Duncan Laurie
2015-09-16
Move final Intel chipsets with ME to intel/common/firmware
Martin Roth
2015-09-09
x86: bootblock: remove linking and program flow from build system
Aaron Durbin
2015-08-31
soc/intel: Fix dependency of CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Alexandru Gagniuc
2015-08-31
soc/intel/braswell/Kconfig: Remove ENABLE_MRC_CACHE Kconfig
Alexandru Gagniuc
2015-08-29
intel/braswell: remove CBFS_SIZE option in SoC directory
Aaron Durbin
2015-07-06
Braswell: Update to end of June.
Lee Leahy
2015-07-04
Kconfig: Fix references to obsolete symbols
Martin Roth
2015-06-25
Braswell: Add Braswell SOC support
Lee Leahy
2015-06-24
Kconfig: Get rid of obsolete symbols
Martin Roth
2015-06-23
Kconfig: Move CBFS_SIZE into Mainboard menu
Martin Roth
2015-05-28
smm: Merge configs SMM_MODULES and SMM_TSEG
Vladimir Serbinenko
2015-05-23
Braswell: Use Baytrail as Comparison Base
Lee Leahy