coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-01-10	Untangle CBFS microcode updates	Nico Huber
2018-12-30	arch/x86: Use a common timestamp.inc with romcc bootblocks	Kyösti Mälkki
2018-12-24	soc/intel/*: Select SUPPORT_CPU_UCODE_IN_CBFS only once	Arthur Heymans
2018-11-21	soc/intel/braswell: Disable OS use of HPET	Frans Hendriks
2018-11-16	soc/intel/braswell: add vmx support via CPU_INTEL_COMMON	Matt DeVillier
2018-10-22	intel: Use CF9 reset (part 2)	Patrick Rudolph
2018-09-13	src/*/intel/: clarify Kconfig options regarding IFD	Stefan Tauner
2018-08-13	soc/intel/braswell/Kconfig: Clean up redefined config options	Arthur Heymans
2018-06-06	arch/x86: Make RELOCATABLE_RAMSTAGE the default	Kyösti Mälkki
2018-03-30	soc/intel/common/opregion: Get rid of opregion.c	Patrick Rudolph
2017-09-30	soc/intel/braswell/acpi: Clean OpRegion up	Patrick Rudolph
2017-08-25	soc/intel/braswell: select GENERIC_GPIO_LIB	Matt DeVillier
2017-08-03	soc/intel/braswell/Kconfig: select RELOCATABLE_RAMSTAGE	Matt DeVillier
2017-06-16	soc/intel/braswell: Hide some Kconfig options in menuconfig	Arthur Heymans
2017-06-08	fsp/gop: Add running the GOP to the choice of gfx init	Nico Huber
2017-03-28	vboot: Select SoC-specific configuration for all Chrome OS boards	Julius Werner
2016-12-07	MMCONF_SUPPORT: Flip default to enabled	Kyösti Mälkki
2016-11-22	Remove explicit select MMCONF_SUPPORT	Kyösti Mälkki
2016-11-08	intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE	Kyösti Mälkki
2016-08-19	Kconfig: introduce writable boot device notion	Aaron Durbin
2016-08-08	chromeos chipsets: select RTC usage	Aaron Durbin
2016-07-31	src/soc: Capitalize CPU, ACPI, RAM and ROM	Elyes HAOUAS
2016-07-15	soc/intel/braswell: use common Intel ACPI hardware definitions	Aaron Durbin
2016-05-06	soc/intel: indicate to build system that XIP_ROM_SIZE isn't used	Aaron Durbin
2016-05-04	cpu/x86: remove BACKUP_DEFAULT_SMM_REGION option	Aaron Durbin
2016-02-12	timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION Kconfig	Julius Werner
2016-01-28	Braswell: Separate L1 Sub State init procedure for boards.	Kenji Chen
2016-01-07	intel/braswell: Disable IFD & ME by default so abuild can build	Martin Roth
2015-10-27	FSP1_1: Always use common code	Lee Leahy
2015-10-27	FSP 1.1: Move common FSP code	Lee Leahy
2015-10-05	Add EM100 'hyper term' spi console support in ramstage & smm	Martin Roth
2015-09-17	braswell: Switch to using common ACPI _SWS code	Duncan Laurie
2015-09-16	Move final Intel chipsets with ME to intel/common/firmware	Martin Roth
2015-09-09	x86: bootblock: remove linking and program flow from build system	Aaron Durbin
2015-08-31	soc/intel: Fix dependency of CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM	Alexandru Gagniuc
2015-08-31	soc/intel/braswell/Kconfig: Remove ENABLE_MRC_CACHE Kconfig	Alexandru Gagniuc
2015-08-29	intel/braswell: remove CBFS_SIZE option in SoC directory	Aaron Durbin
2015-07-06	Braswell: Update to end of June.	Lee Leahy
2015-07-04	Kconfig: Fix references to obsolete symbols	Martin Roth
2015-06-25	Braswell: Add Braswell SOC support	Lee Leahy
2015-06-24	Kconfig: Get rid of obsolete symbols	Martin Roth
2015-06-23	Kconfig: Move CBFS_SIZE into Mainboard menu	Martin Roth
2015-05-28	smm: Merge configs SMM_MODULES and SMM_TSEG	Vladimir Serbinenko
2015-05-23	Braswell: Use Baytrail as Comparison Base	Lee Leahy