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2021-02-11ACPI: Move PICM declarationKyösti Mälkki
Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb,soc/intel: Drop OSYS from GNVSKyösti Mälkki
The value should be set by OSPM using some combination of _OSI() queris in the \_SB._INI() method. To maintain previous behaviour with this commit, boards where GNVS osys initialisation was removed now do the same in ASL. Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11mainboards: Drop PWRS from GNVSKyösti Mälkki
Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-08soc/intel/{baytrail,broadwell}: Add missing <cbmem.h>Angel Pons
Change-Id: Ic4e55f8233e5cb5cea575ad0581adf457a45ba9a Fixes: commit 0322bc5ed8 (src: Remove unused <cbmem.h>) Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50375 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06sb,soc/intel: Add wake source fields in GNVSKyösti Mälkki
For the moment, these are most not used but become a necessity for a unified <soc/nvs.h> approach. They would be required for the implementation of _SWS method for OSPM to determine the reason for system waking up. The related hardware registers are present with these platforms. It's expected that ACPI power-management related GNVS entries are grouped together to form a single struct in later works. Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03src: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-02soc/intel/baytrail,braswell: Drop TOLM from GNVSKyösti Mälkki
It's a static value that is neither referenced from SMI handler nor needs to be updated on S3 resume path. Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50121 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-02soc/intel/baytrail,braswell: Sync PCI memory region in ASLKyösti Mälkki
Baytrail had (only) occurence of DwordMemory vs DWordMemory. Braswell one had bogus comments about the PCI memory range. The actual region details are dynamically filled in _CRS. Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01src: Remove unused <cpu/x86/smm.h>Elyes HAOUAS
Change-Id: Ic3f85a8fbc6a84074f45d94514e1dcfa78cb0958 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-30soc/intel/{baytrail,broadwell} Fix building with refcode blobsAngel Pons
Because the refcode blobs are not redistributable, refcode.c is not build-tested. Commit 6271dd8459 (soc/intel/baytrail,broadwell: Use resume_from_stage_cache()) broke building with refcode blobs. Fix a variable redeclaration error by swapping the order of the code, and use consistent names for the variables. Change-Id: Ic8dda8d35086d977b536686e8c80b7961c37860c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-30soc/amd,intel: Drop leftover GNVS includesKyösti Mälkki
Change-Id: Ia55d53a9a40846db335aabbe4df8e87f6172f712 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once. Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29soc/intel: Drop CMEM from GNVSKyösti Mälkki
Already tagged as obsolete_cmem in <soc/nvs.h> files. Change-Id: I8ba2a79f866fa07f1b4ae7291c72c91db5027911 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50043 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29soc/intel/baytrail,broadwell: Use resume_from_stage_cache()Kyösti Mälkki
Change-Id: Ie7b8bd02c3bb92c6ab9071941abbd90afef82601 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28ACPI: Separate ChromeOS NVS in ASLKyösti Mälkki
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there is reduced dsdt.aml size and reduced GNVS allocation from cbmem. More importantly, it's less error-prone when the OperationRegion size is not hard-coded inside the .asl files. Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28ACPI: Declare GNVS variables globallyKyösti Mälkki
There is a common place where acpigen generates these, so the declarations for the OperationRegions should be centralized too. Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27ACPI: Separate device_nvs_tKyösti Mälkki
Remove typedef device_nvs_t and move struct device_nvs outside of global_nvs. Also remove padding and the reserve for chromeos_acpi_t. Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-25sb,soc/intel: Remove no-op APMC for C-state and P-stateKyösti Mälkki
Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49250 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25cpu/x86/smm: Use common APMC loggingKyösti Mälkki
Unify the debug messages on raised SMIs. Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23soc/intel/baytrail,broadwell: Use bootstate for save_wake_source()Kyösti Mälkki
Change-Id: I01be1b9dfefcfcf037de4153e9540c7258dc160f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49818 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23ACPI: Add helpers for CBMEM_ID_POWER_STATEKyösti Mälkki
Create uniform logging for the (unlikely) case of a CBMEM entry disappearing. Change-Id: I7c5414a03d869423c8ae5192a990fde5f9582f2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-23intel/baytrail,braswell,broadwell: Add const qualifier for power_stateKyösti Mälkki
Change-Id: I37781c1423b49130ffd0d5f9fbdd28a36c9c6179 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-22soc/intel/baytrail,broadwell: Refactor acpi_wake_source()Kyösti Mälkki
Change-Id: I5c277a4b8536fd79bda040d4ada9b0c454399b09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49356 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-20ACPI GNVS: Drop most dev_count_cpu()Kyösti Mälkki
Only amd/picasso and amd/stoneyridge have reference to PCNT and that could be replaced with acpigen. Remove the PCNT name from GNVS OperationRegion elsewhere. Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18ACPI: Refactor ChromeOS specific ACPI GNVSKyösti Mälkki
The layout of GNVS has expectation for a fixed size array for chromeos_acpi_t. This allows us to reduce the exposure of <chromeos/gnvs.h>. If chromeos_acpi_t was the last entry in struct global_nvs padding at the end is also removed. If device_nvs_t exists, place a properly sized reserve for chromeos_acpi_t in the middle. Allocation from cbmem is adjusted such that it matches exactly the OperationRegion size defined inside the ASL. Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-15cpu/x86/mpinit: Serialize microcode updates for HT threadsPatrick Rudolph
This change affects Intel CPUs only. As most platforms are doing uCode update using FIT, they aren't affected by this code either. Update microcode in MP-init using a single spinlock when running on a Hyper-Threading enabled CPU on pre FIT platforms. This will slow down the MP-init boot flow. Intel SDM and various BWGs specify to use a semaphore to update microcode on one thread per core on Hyper-Threading enabled CPUs. Due to this complex code would be necessary to determine the core #ID, initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2. Instead use the existing global spinlock already present in MPinit code. Assuming that only pre-FIT platforms with Hyper-Threading enabled and at most 8 threads will ever run into this condition, the boot delay is negligible. This change is a counterproposal to the previous published patch series being much more unsophisticated. Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-13ACPI: Have single call-site for acpi_inject_nvsa()Kyösti Mälkki
Change-Id: I61a9b07ec3fdaeef0622df82e106405f01e89a9e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48719 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13ACPI: Add common acpi_fill_gnvs()Kyösti Mälkki
Change-Id: I515e830808a95eee3ce72b16fd26da6ec79dac85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48718 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Add missing include in nvs.hKyösti Mälkki
Change-Id: Ic779a668ebaa4f0c9bdef95fd6de8f0179e8a534 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49004 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10soc/intel: Replace acpi_init_gnvs()Kyösti Mälkki
Rename these to soc_fill_gnvs() and move the callsite away from mb/. Change-Id: I760c36f65c6122103f2be98fc11ee13832c2772e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48716 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/x/acpi_tables: Rename to mainboard_fill_gnvs()Kyösti Mälkki
Rename acpi_create_gnvs() functions under mb/ to reflect their changed functionality. Remove now empty mb/acpi_tables.c files. Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Replace uses of CBMEM_ID_ACPI_GNVSKyösti Mälkki
Change-Id: I45a2d9cb7f07609a1ff03fd70f17c3f2d4f013b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant ChromeOS setup for GNVSKyösti Mälkki
Already done in common gnvs_get_or_create() implementation once gnvs_chromeos_ptr() is defined for platforms. Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant CONSOLE_CBMEM setup in GNVSKyösti Mälkki
Already done from common gnvs_get_or_create() implementation after gnvs_cbmc_ptr() is defined. Change-Id: I77c292cd9590d7fc54d8b21ea62717a2d77e5ba4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48702 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocationsKyösti Mälkki
Allocation now happens prior to device enumeration. The step cbmem_add() is a no-op here, if reached for some boards. The memset() here is also redundant and becomes harmful with followup works, as it would wipe out the CBMEM console and ChromeOS related fields without them being set again. Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04arch/x86: Pass GNVS as parameter to SMM moduleKyösti Mälkki
Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04soc/intel/baytrail/southcluster.asl: Use consistent comment formattingMatt DeVillier
Change-Id: I479e1eb5819c42621e8b17367b964124d5433378 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04soc/intel/baytrail: add LPEA resources to southcluster.aslMatt DeVillier
The LPEA device memory resources, required by Windows drivers, were not being set. Allocate required resources using soc/intel/braswell/acpi/southcluster.asl as a reference. This patch alone is not sufficient for working audio under Windows on Baytrail ChromeOS devices, but it is a necessary component. Test: boot Windows 10 on google/swanky, observe LPEA device working properly. Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48745 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03soc/intel: Drop indirect <soc/nvs.h> includeKyösti Mälkki
Change-Id: Ia19018685749efdd543cb09c06df117690ab9d66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48803 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03soc/intel: Replace <soc/nvs.h> with <soc/device_nvs.h>Kyösti Mälkki
Change-Id: Ib78e746875e330e47540a6199343be62aa7e92a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48830 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30drivers/intel/gma: Include gfx.asl by default for all platforms...Matt DeVillier
which select INTEL_GMA_ACPI. Rework brightness level includes and platform-level asl files to avoid duplicate device definition for GFX0. Include gfx.asl for Skylake/Kabylake, since all other soc/intel/common platforms already do. Adjust mb/51nb/x210 to prevent device redefinition. Some OSes (e.g. Windows, MacOS) require/prefer the ACPI device for the IGD to exist, even if ACPI brightness controls are not utilized. This change adds a GFX0 ACPI device for all boards whose platforms select INTEL_GMA_ACPI without requiring non-functional brightness controls to be added at the board level. Change-Id: Ie71bd5fc7acd926b7ce7da17fbc108670fd453e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-22sb,soc/intel: Drop unnecessary headersKyösti Mälkki
Files under sb/ or soc/ should not have includes that tie those directly to external components like ChromeEC os ChromeOS vendorcode. Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03src: Remove redundant use of ACPI offset(0)Elyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26src: Include <arch/io.h> when appropriateElyes HAOUAS
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13src: Rename EM100Pro-specific SPI console Kconfig optionAngel Pons
To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this option with `EM100Pro`. Looks like it is not build-tested, however. Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-02drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-26arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons
Nearly every x86 platform uses the same arch for all stages. The only exception is Picasso. So, factor out redundant symbols from the rest. Alder Lake is not yet complete, so it has been skipped for now. Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-21src/soc/intel: Drop unneeded empty linesElyes HAOUAS
Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08soc/intel/baytrail: Add missing GSM size definitionsAngel Pons
Change-Id: I456591f63f463c5cec1cbf3c1633bdb61be92d29 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44935 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mrc_cache: Add mrc_cache fetch functions to support non-x86 platformsShelley Chen
Create two new functions to fetch mrc_cache data (replacing mrc_cache_get_current): - mrc_cache_load_current: fetches the mrc_cache data and drops it into the given buffer. This is useful for ARM platforms where the mmap operation is very expensive. - mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a given buffer. This is useful for platforms where the mmap operation is a no-op (like x86 platforms). As the name mentions, we are not freeing the memory that we allocated with the mmap, so it is the caller's responsibility to do so. Additionally, we are replacing mrc_cache_latest with mrc_cache_get_latest_slot_info, which does not check the validity of the data when retrieving the current mrc_cache slot. This allows the caller some flexibility in deciding where they want the mrc_cache data stored (either in an mmaped region or at a given address). BUG=b:150502246 BRANCH=None TEST=Testing on a nami (x86) device: reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21SMM: Validate more user-provided pointersPatrick Rudolph
Mitigate issues presented in "Digging Into The Core of Boot" found by "Yuriy Bulygin" and "Oleksandr Bazhaniuk" at RECON-MTL-2017. Validate user-provided pointers using the newly-added functions. This protects SMM from ring0 attacks. Change-Id: I8a347ccdd20816924bf1bceb3b24bf7b22309312 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-18elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPEAaron Durbin
The wake source macro for GPE events was using 'GPIO'. However, current usage is really all GPEs. Therefore, provide clarity in the naming in order to allow for proper GPIO wake events that are separate from the ACPI GPE block. BUG=b:159947207 Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-18src: Remove unused 'include <stddef.h>Elyes HAOUAS
Change-Id: Iae1e875b466f8a195653d897efa1b297c61ad0a5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41912 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05{sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out codeAngel Pons
This code has been commented out for a long time. Drop it. Change-Id: Iddc635dc5bbc7a8b42e97f4e2f6d579a839d874b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43264 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04soc/intel/baytrail: Factor out `acpi_fill_madt()`Angel Pons
It is the same for the two Bay Trail boards in the tree. Change-Id: I5110cfa8807406232e4f7f1fe79dfe9c3ae4dac4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
2020-08-03soc/intel/baytrail: Add MRC SMBus workaroundMate Kukri
- The Bay Trail MRC fails to read the SPDs from SMBus. - Instead the SPDs are read into a buffer and the buffer is passed to the MRC. Change-Id: I7f560d950cb4e4d118f3ee17e6e19e14cd0cc193 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44092 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02soc/intel/baytrail/northcluster.c: Clean up commentsAngel Pons
Giant commit aee7ab2 (soc/intel/braswell: Clean up) reformatted comments to follow the coding style, among many other things. This commit updates some comments on Bay Trail with two objectives: follow the coding style, and reduce the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ibe942a20c624e2c74801c8816616ec83851949af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-08-02soc/intel/baytrail/sata.c: Fix SATA init sequenceAngel Pons
SeaBIOS on Bay Trail would time out when trying to access a SATA drive. Turns out that there's two mistakes in the SATA initialization sequence: - PCI register 0x94 is wrongly cleared with a bitwise-and operation. - PCI register 0x9c is instead written to 0x98, clobbering the latter. After correcting them, SeaBIOS can boot from SATA on Asrock Q1900M. Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44088 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02soc/intel/baytrail: Add native refcode replacementMate Kukri
- This is a reverse engineered re-implementation of refcode.elf on Bay Trail - Tested on GBYT4, should work everywhere as it's meant to behave exactly the same as the binary refcode Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I91977c509022b0078804dc151d27296260e24bc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43133 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02soc/intel/baytrail/northcluster.c: Rename variableAngel Pons
Tested with BUILD_TIMELESS=1, Google Ninja does not change. Change-Id: I7e74f342c0545f8d2a2128de4162581e5dc01e17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02soc/intel/baytrail/northcluster.c: Tidy up long linesAngel Pons
These now fit in 96 characters. Tested with BUILD_TIMELESS=1, Google Ninja does not change. Change-Id: I7e1dc0126fa4d64f75e686d68c4f70f7109c6da0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-26src: Remove whitespace between 'sizeof' and '('Elyes HAOUAS
Change-Id: Iaf22dc1986427e8aa4521b0e9b40fafa5a29dbbd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bitsAngel Pons
We have definitions for the bits in the PCI COMMAND register. Use them. Also add spaces around bitwise operators, to comply with the code style. Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-26cpu,soc/intel: Drop select SMPKyösti Mälkki
Implicitly selected with MAX_CPUS != 1. Change-Id: I4ac3e30e9f96cd52244b4bae73bafce0564d41e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25soc/intel/baytrail/southcluster.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I49e9cef1dfaa62dcfbd1260cec459ff5910ad5da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43202 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/include/soc/irq.h: Add bracesAngel Pons
This reduces the differences between Bay Trail and Braswell, and avoids unlikely but potential bugs regarding missing braces in macros. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ic341fe70e7d6fb4751f2fefbdedbee5c90dd8d1f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43201 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail: Simplify pattrs definitionsAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I90632909cd7d632d80739b3762e4ccba51624b75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43200 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/smm.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Iaf557caac16b36e356a4fb1b05416718d86093bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43199 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/smihandler.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Iaa6d5d72cd0368342205a9b98552c1e0762abbce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43198 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/cpu.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I9d9edd774143b0a98773b6d5de630d116cb6f0b1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43197 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/sd.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I08ccbc70744a17d589450e321a3ed77d9a56492f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43196 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/lpss.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I98d17fc470149b181e8d92b8bcc5d99c68299212 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43195 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/lpe.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: If75b4299918f5bee3cc68bc662d03f1a819aef68 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43194 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/{baytrail,braswell}: Drop unneeded `return`Angel Pons
There's no reason to return the result of a void function. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I677dec1622768874a51effd6d73f0b2329f27aed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43193 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/iosf.c: Add missing bracesAngel Pons
This reduces the differences between Bay Trail and Braswell, and prevents possible bugs when using these macros. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I18e9a750901f1bf8d3b61f4b64bbed907bc1fa15 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43192 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/elog.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ifd71881e3924dca3add1e788852e7eb078405d00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43191 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/cpu.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I52d58c6b77cd870b5d3f5892521e4c82027c4cac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43190 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/acpi.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I0b07f8d52203c0a6d20b747f36d4d22cf53c791c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-25soc/intel/baytrail/bootblock/bootblock.c: Move functionsAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I34079985e165ce8d10c7a2b4f0dde15060132208 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43188 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail: Retype some pointersAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21src: Use ACPI macrosElyes HAOUAS
Change-Id: I2cf11b784299708f02fd749dcb887b6d25f86f5b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-21soc/intel/baytrail: Add new CPUID 0x30679Mate Kukri
This ID is reported by newer mfg date SOCs. Needed for newer GBYT4 boards. Change-Id: I6af746d66a15f67553de1dc1c925e5cb0b181898 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-20src: Report word-sized access for PM1a_EVTAngel Pons
According to the ACPI specification, version 6.3: Accesses to the PM1 status registers are done through byte or word accesses. The same is said about the PM1 Enable registers. Therefore, reporting dword-sized access is wrong and means nothing anyway. Since some other platforms use word-sized access, use word everywhere for consistency. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: I6f85c9a4126f37ab2a193c3ab50a6c8e62cf6515 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43432 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Make HAVE_CF9_RESET set the FADT reset registerAngel Pons
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as reset register in FADT. How unsurprising. We might as well use that information to automatically fill in the FADT accordingly. So, do it. To avoid having x86-specific code under arch-agnostic `acpi/`, create a new optional `arch_fill_fadt` function, and override it for x86 systems. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-20src: Drop useless cache flush settings in FADTAngel Pons
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required on current ACPI versions and only maintained for ACPI 1.0 compatibility. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-20src: Never overwrite `fadt->flags`Angel Pons
Instead, just flip the desired bits using bitwise operations. As this is initially zero, the resulting value is the same. This allows flags to be set from anywhere regardless of execution order. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Drop useless PM1b settings from FADTAngel Pons
None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event register blocks. According to the ACPI specification, version 6.3, sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers): If the PM1b_EVT_BLK is not supported, its pointer contains a value of zero in the FADT. If the PM1b_CNT_BLK is not supported, its pointer contains a value of zero in the FADT. Since the FADT struct defaults to zero in coreboot, we don't need to do anything with PM1b for now. So, drop unneeded writes to PM1b fields. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Drop useless GPE1 settings from FADTAngel Pons
None of the currently-supported chips has a GPE1 block. The ACPI spec, version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says: If a generic register block is not supported then its respective block pointer and block length values in the FADT table contain zeros. Since the FADT struct defaults to zero in coreboot, we don't need to do anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14soc/intel/baytrail: Move `acpi_fill_fadt` to fadt.cAngel Pons
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is needed outside acpi.c with this change. Change-Id: I702988493e3b29d807a75c70485baaa2ff6d1aa2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-14src: Drop unused <cpu/x86/tsc.h> includeElyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/x86/tsc.h>' -- src/) <(git grep -l 'TSC_SYNC\|tsc_struct\|rdtsc\|tsc_t\|multiply_to_tsc\|rdtscll\|tsc_to_uint64\|tsc_freq_mhz\|tsc_constant_rate' -- src/)|grep '<' Change-Id: Id090e232a96323adb8d9a24b81f7ae5669248f57 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42393 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14soc/intel/baytrail/northcluster.c: Add missing includeElyes HAOUAS
Replace unused <stddef.h> with missing <stdint.h>. Change-Id: I85745c331c81a419cef4547fc1c67bde1e202e8f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43346 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14soc/intel/baytrail/romstage/pmc.c: Add missing includeElyes HAOUAS
Replace unused <stddef.h> with missing <stdint.h>. Change-Id: If8384f4fea66e26d7377311e7bd8379c7848a26f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43345 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14soc/intel/baytrail/romstage/raminit.c: Add missing includeElyes HAOUAS
Replace unused <stddef.h> with missing <stdint.h>. Change-Id: I659a067e3b737dc7efe5bdadfd88207cd4d7175d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43344 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controllerMate Kukri
- Correctly detect device 17h as the MMC 4.5 controller - Support detection of the "old" MMC controller at device 10h Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I9f0007b1cf01df09f775c088397c3b9c846908c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-09soc/intel/baytrail/pmutil.c: Constify string arraysAngel Pons
This reduces the differences between Bay Trail and Braswell. The resulting binary changes, but it shouldn't matter. Change-Id: Ic930ab7eee265e86a7cc1095021e3744885f2c25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-07-09soc/intel/baytrail/pmutil.c: Do not hardcode num_bitsAngel Pons
This can result in accesses outside array bounds. Copy what Braswell does, which is slightly safer. Change-Id: If3d6f4e1f8921f0be7f4e5e438b7e73c46b8ef95 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-07-09soc/intel/baytrail: Align whitespace and commentsAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-09soc/intel/baytrail: Rename "pmc.h" to "pm.h"Angel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 23:02:54 +0000