summaryrefslogtreecommitdiff
path: root/src/soc/intel/baytrail
AgeCommit message (Expand)Author
2016-07-15soc/intel/baytrail: use common Intel ACPI hardware definitionsAaron Durbin
2016-07-10intel post-car: Consolidate choose_top_of_stack()Kyösti Mälkki
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
2016-06-18intel cache_as_ram: Fix typo in commentKyösti Mälkki
2016-06-17Fix some cbmem.h includesKyösti Mälkki
2016-05-06soc/intel: indicate to build system that XIP_ROM_SIZE isn't usedAaron Durbin
2016-05-06{cpu,soc}/intel: remove unused smm_init() functionAaron Durbin
2016-05-04soc/intel/baytrail: convert to using common MP and SMM initAaron Durbin
2016-05-04cpu/x86: remove BACKUP_DEFAULT_SMM_REGION optionAaron Durbin
2016-05-03intel/baytrail: use fmap information for code cachingPatrick Georgi
2016-05-02cpu/x86/mp_init: remove unused callback argumentsAaron Durbin
2016-04-14soc/intel: Update license headersMartin Roth
2016-03-08x86 chipsets: utilize x86_setup_mtrrs_with_detect()Aaron Durbin
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
2015-12-10ACPI: Fix IASL Warning about unused method for GBUF checkMartin Roth
2015-12-10lib: remove assets infrastructureAaron Durbin
2015-11-28baytrail: fix missing brackets around ir_base to fix IRQ routingAlexander Couzens
2015-11-24intel/soc/baytrail: Move MCRS ResourceTemplate out of _CRS methodMartin Roth
2015-11-21baytrail: add C0 and D0 stepping decodeBen Gardner
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-10-05Add EM100 'hyper term' spi console support in ramstage & smmMartin Roth
2015-09-30cpu: microcode: Use microcode stored in binary formatAlexandru Gagniuc
2015-09-29intel: auto include intel/common/firmwareAaron Durbin
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
2015-09-23chromeos: vboot and chromeos dependency removal for sw write protect statePaul Kocialkowski
2015-09-09x86: bootblock: remove linking and program flow from build systemAaron Durbin
2015-09-07Drop "See file CREDITS..." commentStefan Reinauer
2015-09-04bootstate: remove need for #ifdef ENV_RAMSTAGEAaron Durbin
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
2015-07-02Move baytrail & fsp_baytrail to the common IFD interface.Martin Roth
2015-06-24Kconfig: Get rid of obsolete symbolsMartin Roth
2015-06-23Kconfig: Move CBFS_SIZE into Mainboard menuMartin Roth
2015-06-09stage_cache: use cbmem init hooksAaron Durbin
2015-06-09cbmem: add indicator to hooks if cbmem is being recoveredAaron Durbin
2015-06-09cbmem: Unify CBMEM init tasks with CBMEM_INIT_HOOK() APIKyösti Mälkki
2015-06-08Remove empty lines at end of fileElyes HAOUAS
2015-06-05device_ops: add device_t argument to acpi_fill_ssdt_generatorAlexander Couzens
2015-06-05device_ops: add device_t argument to acpi_inject_dsdt_generatorAlexander Couzens
2015-06-04devicetree: Change scan_bus() prototype in device opsKyösti Mälkki
2015-06-04devicetree: Discriminate device ops scan_bus()Kyösti Mälkki
2015-06-02assets: abstract away the firmware assets used for bootingAaron Durbin
2015-06-02cbfs: new API and better program loadingAaron Durbin
2015-05-29chromeos: always enable timestampsStefan Reinauer
2015-05-28smm: Merge configs SMM_MODULES and SMM_TSEGVladimir Serbinenko
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
2015-05-26acpi: Remove monolithic ACPIVladimir Serbinenko
2015-05-23baytrail: Switch to per-device ACPIVladimir Serbinenko
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-05-13baytrail: broadwell: correct refcode loadingAaron Durbin
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
2015-05-053rdparty: Move to blobsPatrick Georgi
2015-05-01intel: Correct MMIO related ACPI table settingsDave Frodin
2015-04-30kbuild: Don't require intel/common changes for every socStefan Reinauer
2015-04-29kbuild: automatically include SOCsStefan Reinauer
2015-04-22coreboot: common stage cacheAaron Durbin
2015-04-15soc/baytrail: Use microcode from the blobs repositoryMarc Jones
2015-04-10baytrail: correct NC pin to GPO pin according to BYT platform design guideKane Chen
2015-04-10baytrail: add code for supporting 2x ddr refresh rateKane Chen
2015-04-10baytrail: fix the coding error on PCIe L1 exit latencyKevin L Lee
2015-04-10Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 msKevin Hsieh
2015-04-10baytrail: Switch from ACPI mode to PCI mode for legacy supportMarc Jones
2015-04-07baytrail: Change all SoC headers to <soc/headername.h> systemJulius Werner
2015-04-06baytrail: Fix hdmi audio choppy issueKein Yuan
2015-04-06baytrail: reinitialize spi controller in SMM finalizationAaron Durbin
2015-04-04Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.Kenji Chen
2015-04-03rmodule: use struct prog while loading rmodulesAaron Durbin
2015-04-02baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPUKein Yuan
2015-04-02Baytrail: Change PCIe root disable algorithmKenji Chen
2015-04-02Baytrail: add _PRT to each PCIe root port deviceTed Kuo
2015-04-01cbfs: correct types used for accessing filesAaron Durbin
2015-03-30baytrail: fix HAVE_REFCODE_BLOB build errorsAaron Durbin
2015-03-30Update hex values to CBFS binary name types in MakefilesMartin Roth
2015-03-18bootstate: use structure pointers for scheduling callbacksAaron Durbin
2015-03-10ACPI: Get S3 resume state from romstage_handoffKyösti Mälkki
2015-03-09coreboot: fix munged license textAaron Durbin
2015-02-25soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`Paul Menzel
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
2015-01-27CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki
2015-01-27vboot2: add verstageStefan Reinauer
2015-01-16baytrail: there is a chance that USBPHY_COMPBG is set to 0Kane Chen
2015-01-16baytrail: use the setting in devicetree.cb to config USBPHY_COMPBGKane Chen
2015-01-14baytrail broadwell: Use timestamps internal stashKyösti Mälkki
2015-01-05timestamps: Switch from tsc_t to uint64_tStefan Reinauer
2014-12-31baytrail: add more gpio init macrosKane Chen
2014-12-30baytrail: Add defines and functions for GPNCOREKein Yuan
2014-12-28intel baytrail broadwell: Include microcode updatesKyösti Mälkki
2014-12-19baytrail SOCs: Add missing comma in gpio.hMartin Roth
2014-12-17baytrail: initialize backlight PWM frequencyAaron Durbin
2014-12-17x86: Initialize SPI controller explicitly during PCH initDavid Hendricks
2014-12-09spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.Gabe Black
2014-12-09spi: Remove the spi_set_speed and spi_cs_is_valid functions.Gabe Black
2014-12-08intel/baytrail: Spelling fixesMartin Roth
2014-12-02Replace hlt with halt()Patrick Georgi
2014-11-30Replace hlt() loops with halt()Patrick Georgi
2014-11-25intel: Remove IRQ1 from possible PIRQ assignemnt.Vladimir Serbinenko
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 01:00:46 +0000