coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
	As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA[, ]02110-1301[, ]USA:Foundation, Inc.:" {} + $ find -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]Suite 330, Boston, MA 02111-1307[, ]USA:Foundation, Inc.:" {} + $ find -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \.patch \ -a \! -name \_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-07	baytrail: Change all SoC headers to <soc/headername.h> system	Julius Werner
	This patch aligns baytrail to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Rambi. Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083 Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222026 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-10	baytrail: utilize reg_script_run_on_dev()	Aaron Durbin
	The inclusion of reg_script_run_on_dev() allows for removing some of the chained reg_scripts just to set up the device context. Use the new reg_script function in those cases. BUG=None BRANCH=None TEST=Built and booted. Didn't see any bizarre dmesg or coreboot console output. Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438 Signed-off-by: Aaron Durbin <adurbin@chromium.og> Reviewed-on: https://chromium-review.googlesource.com/179541 Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5009 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10	baytrail: Add support for LPSS and SCC devices in ACPI mode	Duncan Laurie
	This adds the option to put LPSS and SCC devices into ACPI mode by saving their BAR0 and BAR1 base addresses in a new device NVS structure that is placed at offset 0x1000 within the global NVS table. The Chrome NVS strcture is padded out to 0xf00 bytes so there is a clean offset to work with as it will need to be used by depthcharge to know what addresses devices live at. A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and the EMMC 4.5 IRQ is changed to 44. New ACPI code is provided to instantiate the LPSS and SCC devices with the magic HID values from Intel so the kernel drivers can locate and use them. The default is still for devices to be in PCI mode so this does not have any real effect without it being enabled in the mainboard devicetree. Note: this needs the updated IASL compiler which is in the CQ now because it uses the FixedDMA() ACPI operator. BUG=chrome-os-partner:23505,chrome-os-partner:24380 CQ-DEPEND=CL:179459,CL:179364 BRANCH=none TEST=manual tests on rambi device: 1) build and boot with devices still in PCI mode and ensure that nothing is changed 2) enable lpss_acpi_mode and see I2C devices detected by the kernel in ACPI mode. Note that by itself this breaks trackpad probing so that will need to be implemented before it is enabled. 3) enable scc_acpi_mode and see EMMC and SDCard devices detected by the kernel in ACPI mode. Note that this breaks depthcharge use of the EMMC because it is not longer discoverable as a PCI device. Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179481 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5004 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-07	baytrail: initialize common SSC functionality	Aaron Durbin
	The SSC (storage control cluster) houses the SD, SDIO, and eMMC interfaces. The scc cofniguration function, baytrail_init_scc(), is ran in the pre device stage to initialize the SCC. The eMMC is expected to be configured for version 4.5. BUG=chrome-os-partner:23966 BRANCH=None TEST=Built and booted with some other eMMC changes into login screen off of eMMC device. Change-Id: I81cc755a790b7e43ad234a8201dae480277202c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176535 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4966 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>