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Files under sb/ or soc/ should not have includes that tie those
directly to external components like ChromeEC os ChromeOS
vendorcode.
Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file()
to cbfs_map() and cbfs_load() respectively. This is supposed to be the
start of a new, better organized CBFS API where the most common
operations have the most simple and straight-forward names. Less
commonly used variants of these operations (e.g. cbfs_ro_load() or
cbfs_region_load()) can be introduced later. It seems unnecessary to
keep carrying around "boot" in the names of most CBFS APIs if the vast
majority of accesses go to the boot CBFS (instead, more unusual
operations should have longer names that describe how they diverge from
the common ones).
cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly
reap mappings when desired. A few new cbfs_unmap() calls are added to
generic code where it makes sense, but it seems unnecessary to introduce
this everywhere in platform or architecture specific code where the boot
medium is known to be memory-mapped anyway. In fact, even for
non-memory-mapped platforms, sometimes leaking a mapping to the CBFS
cache is a much cleaner solution than jumping through hoops to provide
some other storage for some long-lived file object, and it shouldn't be
outright forbidden when it makes sense.
Additionally, remove the type arguments from these function signatures.
The goal is to eventually remove type arguments for lookup from the
whole CBFS API. Filenames already uniquely identify CBFS files. The type
field is just informational, and there should be APIs to allow callers
to check it when desired, but it's not clear what we gain from forcing
this as a parameter into every single CBFS access when the vast majority
of the time it provides no additional value and is just clutter.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):
- mrc_cache_load_current: fetches the mrc_cache data and drops it into
the given buffer. This is useful for ARM platforms where the mmap
operation is very expensive.
- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
given buffer. This is useful for platforms where the mmap operation
is a no-op (like x86 platforms). As the name mentions, we are not
freeing the memory that we allocated with the mmap, so it is the
caller's responsibility to do so.
Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot. This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).
BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- The Bay Trail MRC fails to read the SPDs from SMBus.
- Instead the SPDs are read into a buffer and the buffer is passed to
the MRC.
Change-Id: I7f560d950cb4e4d118f3ee17e6e19e14cd0cc193
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44092
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We have definitions for the bits in the PCI COMMAND register. Use them.
Also add spaces around bitwise operators, to comply with the code style.
Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Replace unused <stddef.h> with missing <stdint.h>.
Change-Id: I659a067e3b737dc7efe5bdadfd88207cd4d7175d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43344
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Idfb89ceabac6b6906e31a3dbe9096d48ba680599
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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vboot_recovery_mode_enabled() was recently changed to assert() when it
is called before vboot logic has run, because we cannot determine
whether we're going to be in recovery mode at that point and we wanted
to flush out existing uses that pretended that we could. Turns out there
are a bunch of uses like that, and there is some code that is shared
across configurations that can and those that can't.
This patch cleans them up to either remove checks that cannot return
true, or add explicit Kconfig guards to clarify that the code is shared.
This means that using a separate recovery MRC cache is no longer
supported on boards that use VBOOT_STARTS_IN_ROMSTAGE (this has already
been broken with CB:38780, but with this patch those boards will boot
again using their normal MRC caches rather than just die). Skipping the
MRC cache and always regenerating from scratch in recovery mode is
likewise no longer supported for VBOOT_STARTS_IN_ROMSTAGE.
For FSP1.1 boards, none of them support VBOOT_STARTS_IN_BOOTBLOCK and
that is unlikely to change in the future so we will just hardcode that
fact in Kconfig (otherwise, fsp1.1 raminit would also have to be fixed
to work around this issue).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I31bfc7663724fdacab9955224dcaf650d1ec1c3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Populate SMBIOS type 17 tables using data from SPD and read via IOSF.
Refactor print_dram_info() to pass thru SPD data and channel/speed info.
Move call to print_dram_info() after cbmem initialization so the SMBIOS
data has somewhere to go.
Test: build/boot google/swanky, verify via dmidecode.
Change-Id: I1c12b539c78d095713421b93115a4095f3d4278d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ib41169395ab239e520f6047ac6bd307ec50776d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This avoids including platform-specific headers with different
filenames from common code.
Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There's nothing intel-specific about the current mrc_cache support.
It's logic manages saving non-volatile areas into the boot media.
Therefore, expose it to the rest of the system for any and all to
use.
BUG=b:69614064
Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This patch removes checks that ensure EC to be in RO for recovery
boot. We do not need these checks because when recovery is requested
automatically (as opposed to manually), we show 'broken' screen where
users can only reboot the device or request recovery manually.
If recovery is requested, Depthcharge will check whether EC is in RO
or not and recovery switch was pressed or not. If it's a legitimate
manual recovery, EC should be in RO. Thus, we can trust the recovery
button state it reports.
This patch removes all calls to google_chromeec_check_ec_image,
which is called to avoid duplicate memory training when recovery
is requested but EC is in RW.
BUG=b:66516882
BRANCH=none
CQ-DEPEND=CL:693008
TEST=Boot Fizz.
Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Update the mrc cache implementation to use region_file. Instead
of relying on memory-mapped access and pointer arithmetic
use the region_devices and region_file to obtain the latest
data associated with the region. This removes the need for the
nvm wrapper as the region_devices can be used directly. Thus,
the library is more generic and can be extended to work on
different boot mediums.
BUG=chrome-os-partner:56151
Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17717
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.
BUG=chrome-os-partner:55639
Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: Idf055fa86b56001a805e139de6723dfb77dcb224
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15669
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Instead of having the chipset code make the approrpiate
calls at the appropriate places use the cbmem init hooks
to take the appropriate action. That way no chipset code
needs to be changed in order to support the external
stage cache.
Change-Id: If74e6155ae86646bde02b2e1b550ade92b8ba9bb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10481
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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A new CBFS API is introduced to allow making CBFS access
easier for providing multiple CBFS sources. That is achieved
by decoupling the cbfs source from a CBFS file. A CBFS
source is described by a descriptor. It contains the necessary
properties for walking a CBFS to locate a file. The CBFS
file is then decoupled from the CBFS descriptor in that it's
no longer needed to access the contents of the file.
All of this is accomplished using the regions infrastructure
by repsenting CBFS sources and files as region_devices. Because
region_devices can be chained together forming subregions this
allows one to decouple a CBFS source from a file. This also allows
one to provide CBFS files that came from other sources for
payload and/or stage loading.
The program loading takes advantage of those very properties
by allowing multiple sources for locating a program. Because of
this we can reduce the overhead of loading programs because
it's all done in the common code paths. Only locating the
program is per source.
Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9134
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.
Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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This patch aligns baytrail to the new SoC header include scheme.
BUG=None
TEST=Tested with whole series. Compiled Rambi.
Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083
Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/222026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9363
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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In commit 72a8e5e751a7fa97c9d198f68cad49f9d9851669 the
Makefile's were updated to use named types for cbfs
file addition. However, the call sites were not checked to
ensure the types matched. Correct all call sites to use the
named types.
Change-Id: Ib9fa693ef517e3196a3f04e9c06db52a9116fee7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9195
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7606
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Provide the option to embed MRC as an ELF file and not just
binary blob. This allows for MRC to be relocated.
BUG=chrome-os-partner:27654
BRANCH=rambi
TEST=Built and booted rambi.
Change-Id: I2e177c155a3074e4e1d450b1a73b7299aebd5286
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/192893
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 89c97d5e2023b8c5cc780e1b1d532d0a586512f9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7214
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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This common code can be shared across Intel SOCs.
Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196263
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6967
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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rambi: Change RAM_ID GPIOs to GPIO_INPUT
Reviewed-on: https://chromium-review.googlesource.com/182934
(cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0)
baytrail: initialize rtc device
Reviewed-on: https://chromium-review.googlesource.com/183051
(cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821)
baytrail: Set SOC power budget values for SdpProfile 2&3
Reviewed-on: https://chromium-review.googlesource.com/183101
(cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55)
baytrail: Set PMC PTPS register correctly
Reviewed-on: https://chromium-review.googlesource.com/183280
(cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad)
baytrail: update to version 809 microcode for c0
Reviewed-on: https://chromium-review.googlesource.com/183256
(cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e)
baytrail: Add a shared GNVS init function
Reviewed-on: https://chromium-review.googlesource.com/183332
(cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c)
baytrail: Add basic support for ACPI System Wake Source
Reviewed-on: https://chromium-review.googlesource.com/183333
(cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619)
baytrail: allow configuration of io hole size
Reviewed-on: https://chromium-review.googlesource.com/183269
(cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919)
baytrail: add in C0 stepping idenitification support.
Reviewed-on: https://chromium-review.googlesource.com/183594
(cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4)
baytrail: add option for enabling PS2 mode
Reviewed-on: https://chromium-review.googlesource.com/183595
(cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f)
rambi: enable PS2 mode for VNN and VCC
Reviewed-on: https://chromium-review.googlesource.com/183596
(cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9)
baytrail: add config option for disabling slp_x stretching
Reviewed-on: https://chromium-review.googlesource.com/183587
(cherry picked from commit f99804c2649bef436644dd300be2a595659ceece)
rambi: disable slp_x stretching after sus fail
Reviewed-on: https://chromium-review.googlesource.com/183588
(cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880)
baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI
Reviewed-on: https://chromium-review.googlesource.com/183597
(cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906)
rambi: fix trackpad and touchscreen wake sources
Reviewed-on: https://chromium-review.googlesource.com/183598
(cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5)
baytrail: Add support for LPE device in ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/184006
(cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f)
rambi: Add LPE GPIOs for Jack/Mic detect
Reviewed-on: https://chromium-review.googlesource.com/184007
(cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578)
rambi: Set TSRx passive threshold to 60C
Reviewed-on: https://chromium-review.googlesource.com/184008
(cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee)
baytrail: DPTF: Add PPCC object for power limit information
Reviewed-on: https://chromium-review.googlesource.com/184158
(cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b)
baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant
Reviewed-on: https://chromium-review.googlesource.com/184442
(cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd)
rambi: Move the CPU passive/critical threshold config to DPTF
Reviewed-on: https://chromium-review.googlesource.com/184443
(cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac)
baytrail: Fix XHCI controller reset on resume
Reviewed-on: https://chromium-review.googlesource.com/184500
(cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd)
baytrail: update lpe audio firmware location
Reviewed-on: https://chromium-review.googlesource.com/184481
(cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6)
rambi: Put LPSS devices in ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/184530
(cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1)
baytrail: initialize HDA device and HDMI codec
Reviewed-on: https://chromium-review.googlesource.com/184710
(cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961)
baytrail: provide GPIO_ACPI_WAKE configuration
Reviewed-on: https://chromium-review.googlesource.com/184718
(cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b)
rambi: configure wake pins as just wake sources
Reviewed-on: https://chromium-review.googlesource.com/184719
(cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115)
baytrail: I2C: Add config data to ACPI Device
Reviewed-on: https://chromium-review.googlesource.com/184922
(cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8)
Squashed 28 commits for rambi and baytrail.
Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6916
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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This improves boot time in 2 ways for a firmware upgrade:
1. Normally MRC would detect the S0 state without an MRC cache
even though it's told to the S5 path. When it observes this
state a cold reset occurs. The cold reset stays in S5 for
at least 4 seconds which is time observed by the end user.
2. As the EC was running RW code before the reset after firmware
upgrade it will still be running the older RW code. Vboot will
then reboot the EC and the whole system to put the EC into RO
mode so it can handle the RW update.
The issues are mitigated by detecting the system is in S0 with
no MRC cache and the EC isn't in RO mode. Therefore we can do the
reboot without waiting the 4 secs and the EC is running RO so
the 2nd reboot is not necessary.
BUG=chrome-os-partner:24133
BRANCH=rambi,squawks
TEST=Booted. Updated firmware while in OS. Rebooted. Noted the
EC reboot before MRC execution.
Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182061
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5040
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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use IS_ENABLED() over #if brackets
Change-Id: I101f99971c0f7b5311ef19cc9832713ab0696935
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5692
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Add config option to enable RMT in the MRC.
BUG=chrome-os-partner:21807
TEST=Manual. Build w/ "USE=rmt", verify RMT print seen on FW console.
Build w/o USE flag, verify no RMT print.
BRANCH=None.
CQ-DEPEND=CL:*148655
Change-Id: Ibd3da87317a3359e797d9b43bc437e7227a85048
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178095
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4982
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Previously the only path through memory init and coreboot was
hardcoding S5. Therefore all S3 paths would not be taken. Allow
for S3 resume to work by enabling the proper control paths in
romstage.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=While in kernel 'echo mem > /sys/power/state'. Board went
into S3. Power button press resumed back into kernel.
Change-Id: I3cbae73223f0d71c74eb3d6b7c25d1b32318ab3e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175940
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4943
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This gives us completely transparent low-level function to transmit
data.
Change-Id: I706791ff43d80a36a7252a4da0e6f3af92520db7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5336
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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After running the MRC blob print out some information
on the training: MRC version, number channels, DDR3
type, and DRAM frequency.
Example output:
MRC v0.90
2 channels of DDR3 @ 1066MHz
Apparently there are two dunit IOSF ports -- 1 for each
channel. However, certain registers really on live in
channel 0. Thus, there was some changes to dunit support
in the iosf area.
BUG=chrome-os-partner:22875
BRANCH=None
TEST=Built and booted bayleybay in different configs.
Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172770
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4882
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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The mrc_wrapper.h was changed to protect against ABI differences
between the two sets of compilers and flags used. This requires
a prope shim for the console output funciton.
BUG=chrome-os-partner:23048
BRANCH=None
TEST=Built and booted successfully.
Change-Id: I976e692e66dcfc0eacadae6173abfd9b81e31137
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171580
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4858
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The initial Bay Trail code is intended to support
the mobile and desktop version of Bay Trail. This support
can train memory and execute through ramstage. However,
the resource allocation is not curently handled correctly.
The MRC cache parameters are successfully saved and reused
after the initial cold boot.
BUG=chrome-os-partner:22292
BRANCH=None
TEST=Built and booted on a reference board through ramstage.
Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168387
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4847
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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