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Replace unused <stddef.h> with missing <stdint.h>.
Change-Id: If8384f4fea66e26d7377311e7bd8379c7848a26f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43345
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ib41169395ab239e520f6047ac6bd307ec50776d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This moves programming BAR's and setting up console in the bootblock.
Change-Id: I062461cb7bfba2c4df4c20707ecda32f9857b164
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36873
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The function does not otherwise need dev.
Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35670
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0727a6b327410197cf32f598d1312737744386b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Currently, there is a trailing space in the log message below.
> Enabling VR PS2 mode: VNN VCC
So, put the space before the word.
Change-Id: Ic536d77aa910b1b98a3c2f35d595dee4251b1c18
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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This patch aligns baytrail to the new SoC header include scheme.
BUG=None
TEST=Tested with whole series. Compiled Rambi.
Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083
Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/222026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9363
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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rambi: Change RAM_ID GPIOs to GPIO_INPUT
Reviewed-on: https://chromium-review.googlesource.com/182934
(cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0)
baytrail: initialize rtc device
Reviewed-on: https://chromium-review.googlesource.com/183051
(cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821)
baytrail: Set SOC power budget values for SdpProfile 2&3
Reviewed-on: https://chromium-review.googlesource.com/183101
(cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55)
baytrail: Set PMC PTPS register correctly
Reviewed-on: https://chromium-review.googlesource.com/183280
(cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad)
baytrail: update to version 809 microcode for c0
Reviewed-on: https://chromium-review.googlesource.com/183256
(cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e)
baytrail: Add a shared GNVS init function
Reviewed-on: https://chromium-review.googlesource.com/183332
(cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c)
baytrail: Add basic support for ACPI System Wake Source
Reviewed-on: https://chromium-review.googlesource.com/183333
(cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619)
baytrail: allow configuration of io hole size
Reviewed-on: https://chromium-review.googlesource.com/183269
(cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919)
baytrail: add in C0 stepping idenitification support.
Reviewed-on: https://chromium-review.googlesource.com/183594
(cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4)
baytrail: add option for enabling PS2 mode
Reviewed-on: https://chromium-review.googlesource.com/183595
(cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f)
rambi: enable PS2 mode for VNN and VCC
Reviewed-on: https://chromium-review.googlesource.com/183596
(cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9)
baytrail: add config option for disabling slp_x stretching
Reviewed-on: https://chromium-review.googlesource.com/183587
(cherry picked from commit f99804c2649bef436644dd300be2a595659ceece)
rambi: disable slp_x stretching after sus fail
Reviewed-on: https://chromium-review.googlesource.com/183588
(cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880)
baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI
Reviewed-on: https://chromium-review.googlesource.com/183597
(cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906)
rambi: fix trackpad and touchscreen wake sources
Reviewed-on: https://chromium-review.googlesource.com/183598
(cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5)
baytrail: Add support for LPE device in ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/184006
(cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f)
rambi: Add LPE GPIOs for Jack/Mic detect
Reviewed-on: https://chromium-review.googlesource.com/184007
(cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578)
rambi: Set TSRx passive threshold to 60C
Reviewed-on: https://chromium-review.googlesource.com/184008
(cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee)
baytrail: DPTF: Add PPCC object for power limit information
Reviewed-on: https://chromium-review.googlesource.com/184158
(cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b)
baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant
Reviewed-on: https://chromium-review.googlesource.com/184442
(cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd)
rambi: Move the CPU passive/critical threshold config to DPTF
Reviewed-on: https://chromium-review.googlesource.com/184443
(cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac)
baytrail: Fix XHCI controller reset on resume
Reviewed-on: https://chromium-review.googlesource.com/184500
(cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd)
baytrail: update lpe audio firmware location
Reviewed-on: https://chromium-review.googlesource.com/184481
(cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6)
rambi: Put LPSS devices in ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/184530
(cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1)
baytrail: initialize HDA device and HDMI codec
Reviewed-on: https://chromium-review.googlesource.com/184710
(cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961)
baytrail: provide GPIO_ACPI_WAKE configuration
Reviewed-on: https://chromium-review.googlesource.com/184718
(cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b)
rambi: configure wake pins as just wake sources
Reviewed-on: https://chromium-review.googlesource.com/184719
(cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115)
baytrail: I2C: Add config data to ACPI Device
Reviewed-on: https://chromium-review.googlesource.com/184922
(cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8)
Squashed 28 commits for rambi and baytrail.
Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6916
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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The punit is responsible for a number of things. Without
performing the sequence included it won't change processor
frequency when requested and apparently there are some bizarre
hangs introduced if this sequence isn't included either. Lastly,
this needs to come after microcode has been loaded. As that is
done in bootblock the ordering is correct.
One other side effect is that this fixes the graphics devices'
device id. Before it was showing up as the same device id of the
SoC transaction router.
BUG=chrome-os-partner:22880
BUG=chrome-os-partner:23085
BUG=chrome-os-partner:22876
BRANCH=None
TEST=Built and booted.
Change-Id: Ib7be1d4b365e9a45647c778ee5f91de497c55bf1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171862
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4864
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The TCO timer always starts ticking out of reset.
However, depending on microcode loading and punit
initialization the TCO timing out has a different
impact on the sytem. Without loading microcode
or initializing the punit the tco times out and
nothing happens. However, when microcode is loaded
a timeout will reset the system. Lastly, if the
punit is initialized but the microcode isn't loaded
the TCO timeout will shut down the system.
To fix all the weird symptoms disable the TCO.
BUG=chrome-os-partner:22858
BRANCH=None
TEST=Built and booted with microcode loading. Reset doesn't
occur.
Change-Id: I49cd62f510726a96bf734ae728a352c671d1561e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171860
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4862
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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