coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-03-22	soc/intel/{baytrail,braswell}: Make use of generic set_subsystem()	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2018-10-23	src: Remove unneeded whitespace	Elyes HAOUAS
2018-05-24	soc/intel/baytrail: Get rid of device_t	Elyes HAOUAS
2016-08-31	src/soc: Add required space before opening parenthesis '('	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-06-04	devicetree: Change scan_bus() prototype in device ops	Kyösti Mälkki
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-10	baytrail: fix the coding error on PCIe L1 exit latency	Kevin L Lee
2015-04-10	Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 ms	Kevin Hsieh
2015-04-07	baytrail: Change all SoC headers to <soc/headername.h> system	Julius Werner
2015-04-04	Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.	Kenji Chen
2015-04-02	Baytrail: Change PCIe root disable algorithm	Kenji Chen
2014-12-08	intel/baytrail: Spelling fixes	Martin Roth
2014-10-22	baytrail/rambi: S3 support and other updates	Kein Yuan
2014-05-10	baytrail: utilize reg_script_run_on_dev()	Aaron Durbin
2014-05-07	baytrail: pcie: Root port initialization	Aaron Durbin