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path: root/src/soc/intel/baytrail/microcode
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2014-10-01baytrail: update C0 microcodeShawn Nematbakhsh
baytrail: Add 811 microcode for C0 parts Incorporate 811 microcode version for C0 stepping parts. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Old-Change-Id: Ic34c233df28fa2c94db3a886faad8239a05f475d Reviewed-on: https://chromium-review.googlesource.com/191693 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 57c9cbdb9e4bb1cf721849ace8958eb6ec032594) baytrail: Add 813 microcode for C0 parts Incorporate 813 microcode version for C0 stepping parts. Old-Change-Id: I513ce5cc1470fa0154bee088547c5cb8a5902fb5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195200 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit bf15a48c6bd71c2b0ab91530713afb26e139ad9c) baytrail: Update microcode to version 816 Version 816 of microcode. Old-Change-Id: I868702ec94a265013bb5e378a2345ff1cf0dc364 Original-Change-Id: I9a9cacf2d16bdabdb7ec84607bf6c96e4ac3f3c4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197692 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 16512b09e399c05cf42694854277aa7f1753e49e) Squashed 3 successive updates for baytrail C0 microcode. Change-Id: I76714ae636b119348e6bb9f8a4639c68be32ba3a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7000 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-24baytrail: add 80c microcode for C0 partsAaron Durbin
Incoprorate 80c microcode version for C0 stepping parts. Change-Id: I2a76b4c92cac0aca5949313060f1d315ebd8e1a9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187842 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 318027a8853060e7223524dbd2ad7c3b6cc9b766) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-18rambi/baytrail: ACPI, GPIO, audio, misc updatesShawn Nematbakhsh
rambi: Change RAM_ID GPIOs to GPIO_INPUT Reviewed-on: https://chromium-review.googlesource.com/182934 (cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0) baytrail: initialize rtc device Reviewed-on: https://chromium-review.googlesource.com/183051 (cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821) baytrail: Set SOC power budget values for SdpProfile 2&3 Reviewed-on: https://chromium-review.googlesource.com/183101 (cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55) baytrail: Set PMC PTPS register correctly Reviewed-on: https://chromium-review.googlesource.com/183280 (cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad) baytrail: update to version 809 microcode for c0 Reviewed-on: https://chromium-review.googlesource.com/183256 (cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e) baytrail: Add a shared GNVS init function Reviewed-on: https://chromium-review.googlesource.com/183332 (cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c) baytrail: Add basic support for ACPI System Wake Source Reviewed-on: https://chromium-review.googlesource.com/183333 (cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619) baytrail: allow configuration of io hole size Reviewed-on: https://chromium-review.googlesource.com/183269 (cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919) baytrail: add in C0 stepping idenitification support. Reviewed-on: https://chromium-review.googlesource.com/183594 (cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4) baytrail: add option for enabling PS2 mode Reviewed-on: https://chromium-review.googlesource.com/183595 (cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f) rambi: enable PS2 mode for VNN and VCC Reviewed-on: https://chromium-review.googlesource.com/183596 (cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9) baytrail: add config option for disabling slp_x stretching Reviewed-on: https://chromium-review.googlesource.com/183587 (cherry picked from commit f99804c2649bef436644dd300be2a595659ceece) rambi: disable slp_x stretching after sus fail Reviewed-on: https://chromium-review.googlesource.com/183588 (cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880) baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI Reviewed-on: https://chromium-review.googlesource.com/183597 (cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906) rambi: fix trackpad and touchscreen wake sources Reviewed-on: https://chromium-review.googlesource.com/183598 (cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5) baytrail: Add support for LPE device in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184006 (cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f) rambi: Add LPE GPIOs for Jack/Mic detect Reviewed-on: https://chromium-review.googlesource.com/184007 (cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578) rambi: Set TSRx passive threshold to 60C Reviewed-on: https://chromium-review.googlesource.com/184008 (cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee) baytrail: DPTF: Add PPCC object for power limit information Reviewed-on: https://chromium-review.googlesource.com/184158 (cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b) baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant Reviewed-on: https://chromium-review.googlesource.com/184442 (cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd) rambi: Move the CPU passive/critical threshold config to DPTF Reviewed-on: https://chromium-review.googlesource.com/184443 (cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac) baytrail: Fix XHCI controller reset on resume Reviewed-on: https://chromium-review.googlesource.com/184500 (cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd) baytrail: update lpe audio firmware location Reviewed-on: https://chromium-review.googlesource.com/184481 (cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6) rambi: Put LPSS devices in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184530 (cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1) baytrail: initialize HDA device and HDMI codec Reviewed-on: https://chromium-review.googlesource.com/184710 (cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961) baytrail: provide GPIO_ACPI_WAKE configuration Reviewed-on: https://chromium-review.googlesource.com/184718 (cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b) rambi: configure wake pins as just wake sources Reviewed-on: https://chromium-review.googlesource.com/184719 (cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115) baytrail: I2C: Add config data to ACPI Device Reviewed-on: https://chromium-review.googlesource.com/184922 (cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8) Squashed 28 commits for rambi and baytrail. Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6916 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-13baytrail: add C0 microcode updateAaron Durbin
Include C0 microcode drop. BUG=None BRANCH=rambi,squawks TEST=Built. Booted B3 part. Change-Id: If454658235cd5a7b8640de0b3fa12dccddb0e9f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182080 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5041 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-08baytrail: Update to microcode 31E and fix C-state tableDuncan Laurie
With microcode 31E MWAIT 0x51 is now C6NS and 0x52 is now C6FS. BUG=chrome-os-partner:23505 BRANCH=none TEST=build and boot on rambi, check that C1/C2/C3 are all used now Change-Id: I8528d808f4082c85d90e2b57747d9f2e2d982b85 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178461 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4984 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-06baytrail: Add microcode/punit release 31aDuncan Laurie
BUG=chrome-os-partner:23505 BRANCH=none TEST=build and boot on rambi Change-Id: I89c25142245cd268f755210784fd9d0c60dc5661 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176305 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4955 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-24baytrail: add microcode version 319Aaron Durbin
Update microcode version to 319. BUG=None BRANCH=None TEST=Built and booted. Noted 319 being used. Change-Id: I008f90a1c6b542d979e34da22e9f375224c0ffeb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174551 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4900 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-05baytrail: add 316 microcodeAaron Durbin
The 316 microcode is the newest version. Include that in the build. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and partially booted with microcode loading. Noted 316 loaded. Change-Id: Iba01dd58688737ae38bc58a84014ee9526540db1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171611 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4860 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-02Add section header parsing and use it in the mk-payload stepRonald G. Minnich
This completes the improvements to the ELF file parsing code. We can now parse section headers too, across all 4 combinations of word size and endianness. I had hoped to completely remove the use of htonl until I found it in cbfs_image.c. That's a battle for another day. There's now a handy macro to create magic numbers in host byte order. I'm using it for all the PAYLOAD_SEGMENT_* constants and maybe we can use it for the others too, but this is sensitive code and I'd rather change one thing at a time. To maximize the ease of use for users, elf parsing is accomplished with just one function: int elf_headers(const struct buffer *pinput, Elf64_Ehdr *ehdr, Elf64_Phdr **pphdr, Elf64_Shdr **pshdr) which requires the ehdr and pphdr pointers to be non-NULL, but allows the pshdr to be NULL. If pshdr is NULL, the code will not try to read in section headers. To satisfy our powerful scripts, I had to remove the ^M from an unrelated microcode file. BUG=None TEST=Build a peppy image (known to boot) with old and new versions and verify they are bit-for-bit the same. This was also fully tested across all chromebooks for building and booting and running chromeos. BRANCH=None Change-Id: I54dad887d922428b6175fdb6a9cdfadd8a6bb889 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/181272 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/5098 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-31baytrail: update microcode to version 313Aaron Durbin
B2 and B3 steppings are now bumped to version 313. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built. Change-Id: I09ae5110b66c725e959e95fc15bc85ccf371495d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170425 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4848 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-31baytrail: add initial supportAaron Durbin
The initial Bay Trail code is intended to support the mobile and desktop version of Bay Trail. This support can train memory and execute through ramstage. However, the resource allocation is not curently handled correctly. The MRC cache parameters are successfully saved and reused after the initial cold boot. BUG=chrome-os-partner:22292 BRANCH=None TEST=Built and booted on a reference board through ramstage. Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168387 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4847 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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