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2016-10-26soc/intel/apollolake: Enable write-protect SPI flash range supportFurquan Shaikh
Use intel common infrastructure to enable support for write-protecting SPI flash range. Also, enable this protection for RW_MRC_CACHE. BUG=chrome-os-partner:58896 TEST=Verified that write to RW_MRC_CACHE fails in OS using "flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin" Change-Id: I35df12bc295d141e314ec2cb092d904842432394 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17117 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-25Revert "soc/apollolake: Add soc core init"Aaron Durbin
This reverts commit a52f883b100f3229dd4d86c81c08781993861f73 (https://review.coreboot.org/16587). The above commit caused another sever kernel boot regression upwards of 2 minutes to get through kernel init on quad core systems. BUG=chrome-os-partner:58994 Change-Id: Id4abc332bf2266e3b3b7be714371ce9cf329bcd9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17121 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-10-25soc/intel/apollolake: Implement GPIO ACPI AML generating functionsFurquan Shaikh
Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio BUG=chrome-os-partner:55988 Change-Id: I3d8695d73a1c43555032de90f14ee47ccee45559 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17082 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-16soc/apollolake: Add soc core initRavi Sarawadi
Skip FSP initiated core/MP init as it is implemented and initiated in coreboot. Add soc core init to set up the following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST= Check C-state functioning using 'powertop'. Check 0xE2 and 0xE4 MSR to verify IO/Mwait redirection. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767 Reviewed-on: https://review.coreboot.org/16587 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-16soc/intel/apollolake: Set PL1 limits for RAPL MSR registersSumeet Pawnikar
This patch sets the package power limit (PL1) value in RAPL MSR and disables MMIO register. Added configurable PL1 override parameter to leverage full TDP capacity. BUG=chrome-os-partner:56922 TEST=webGL performance(fps) not impacted before and after S3. Change-Id: I34208048a6d4a127e9b1267d2df043cb2c46cf77 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16884 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-16soc/intel/apollolake: clear PMC registersAaron Durbin
The clearing of the PMC registers was not being called resulting in state persisting across reboots. This state is queried and events are added to the eventlog like 'RTC reset' events. However, the RTC reset event is a one time thing so it should only be logged once. Without the clearing of the state the event was logged on every boot. BUG=chrome-os-partner:58496 Change-Id: I60aa7102977c2b1775ab8c54d1c147737d2af5e2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17027 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-07soc/intel/apollolake: Disable HECI2 device reset on S3 resumeAndrey Petrov
Converged Security Engine (CSE) has a secure variable storage feature. However, this storage is expected to be reset during S3 resume flow. Since coreboot does not use secure storage feature, disable HECI2 reset request. This saves appr. 130ms of resume time. BUG=chrome-os-partner:56941 BRANCH=none TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note FspMemoryInit time is not significantly different from normal boot time case. Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16870 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-07soc/intel/apollolake: Implement stage cache to improve resume timeBrandon Breitenstein
This patch enables stage cache to save ~40ms during S3 resume. It saves ramstage in the stage cache and restores it on resume so that ramstage does not have to reinitialize during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16833 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-07Revert "soc/intel/apollolake: Add pmc_ipc device support"Furquan Shaikh
This reverts commit 28821dbb2261267462a7e9b0cc1c23b51af2d3ee. (https://review.coreboot.org/16649) This change causes the kernel to boot really slow. Maybe there is an interrupt storm that prevents the kernel from making any progress. Reverting until the proper kernel dependency is met. BUG=chrome-os-partner:57364 BRANCH=None TEST=Kernels boots to prompt fine on DVT. Change-Id: I1c9913b4476a08303f9dd887b8631601c847dcf7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7014ee1bb88df7a2d7f6b3dced797fef75b252d Original-Change-Id: I061c0b03b43b516a190b370c04888e73a410fcf1 Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/391233 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/16881 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01soc/intel/apollolake: Try to update BSP microcode from cbfsMartin Roth
The microcode for the BSP gets loaded early from the fit table, but in case we have newer microcode in cbfs, try to load it again from cbfs. BUG=chrome-os-partner:53013 TEST=Boot and verify that microcode tries to load into the BSP. Change-Id: Ifd6c78d7b0eec333b79e0fe5cb6a81981b078f5d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16829 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-28soc/intel/apollolake: Add pmc_ipc device supportLijian Zhao
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver. The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and Punit Mailbox. BRANCH=None BUG=chrome-os-partner:57364 TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/16649 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-28soc/intel/apollolake: Use fixed resource for SRAM and IPC1Lijian Zhao
Intel telemetry support will require PMC IPC1 and SRAM devices to be operated in ACPI mode. Then using fixed resources on BAR0, BAR1 and BAR2 (PMC only) for those two devices will help the resource assignment in DSDT stage. BUG=chrome-os-partner:57364 BRANCH=None TEST=Boot up into Chrome OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/16648 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-26soc/intel/apollolake: provide power button ACPI deviceAaron Durbin
Instead of having each mainboard provide the power button, uncondtionally provide the power button ACPI device on behalf of each mainboard. BUG=chrome-os-partner:56677 Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16731 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-22soc/intel/apollolake: Initialize processor count in GNVSDuncan Laurie
Initialize the PCNT variable in GNVS so it is available to ACPI code that expects to know the number of CPUs. Change-Id: I7a6e003ac94218061bf98e8883ed2c62d856af8d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-21soc/apollolake: Correct the comment section in gpio.aslShaunak Saha
This patch corrects the comment section in gpio.asl for GPE method. Change-Id: I45771a295ee1eda00b9699f42cddd120223ff7bf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16647 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21soc/intel/apollolake: Add function to read and clear GPE statusDuncan Laurie
Implement the generic acpi_get_gpe() function to read and clear the GPE status for a specific GPE. Tested by watching GPE status in a loop while generating interrupts manually from the EC console. BUG=chrome-os-partner:53336 Change-Id: I482ff52051a48441333b573f1cd0fa7f7579a6ab Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16671 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21soc/intel/apollolake: Initialize GPEs in bootblockDuncan Laurie
Initialize the GPEs from mainboard config in bootblock, so they can be used in verstage to query latched interrupt status. I still left it called in ramstage just to be sure that the configuration was not overwritten in FSP stages. Tested by reading and reporting GPE status in a loop in verstage and manually triggering an interrupt on EC console. BUG=chrome-os-partner:53336 Change-Id: Iacd0483e4b3229aca602bb5bb40586eedf35a6ea Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16670 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19Revert "soc/intel/apollolake: Initialize GPEs in bootblock"Duncan Laurie
This reverts commit 5e3dad66227bba4be9365ee76d00231bb5577b56.
2016-09-19Revert "soc/intel/apollolake: Add function to read and clear GPE status"Duncan Laurie
This reverts commit 3d43a7c111d00be246160a04023fe438ae0cac57.
2016-09-19soc/intel/apollolake: Add function to read and clear GPE statusDuncan Laurie
Implement the generic acpi_get_gpe() function to read and clear the GPE status for a specific GPE. Tested by watching GPE status in a loop while generating interrupts manually from the EC console. BUG=chrome-os-partner:53336 Change-Id: Id885e98d48c2133a868da19eca3360e2dfb82e84 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19soc/intel/apollolake: Initialize GPEs in bootblockDuncan Laurie
Initialize the GPEs from mainboard config in bootblock, so they can be used in verstage to query latched interrupt status. I still left it called in ramstage just to be sure that the configuration was not overwritten in FSP stages. Tested by reading and reporting GPE status in a loop in verstage and manually triggering an interrupt on EC console. BUG=chrome-os-partner:53336 Change-Id: I1af3e9ac1e5c59b9ebb5c6dd1599309c1f036581 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19soc/intel/apollolake: Configure ACPI name for PCIeVaibhav Shankar
This implements acpi name for PCIe root port. BUG=chrome-os-partner:56483 Change-Id: Ifec1529c477f554d36f3932b66f62eea782fdcaa Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16621 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19soc/intel/apollolake: always enable BOOTBLOCK_CONSOLEAaron Durbin
In order to ensure bootblock console output shows up in cbmem console unconditionally select BOOTBLOCK_CONSOLE. BUG=chrome-os-partner:57513 Change-Id: Ie560dd0e7102c79f6db186a11d6f934505bac116 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16622 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19soc/intel/apollolake: enable postcar consoleAaron Durbin
Unconditionally turn on postcar console for apollolake. BUG=chrome-os-partner:57513 Change-Id: I3d956be4a5834a4721767d34216eebeabef3e315 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16620 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19soc/intel/apollolake: cache boot media post romstageAaron Durbin
When the boot media is memory mapped mark it as cacheable after romstage. Otherwise the boot media is uncacheable and all loads from it take longer. Loading FSP-S alone in ramstage went down to 17.5ms from 54ms. BUG=chrome-os-partner:56656 Change-Id: I6703334ba8fe98aca26ba1c995d6d3abb0ddef33 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16613 Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-15soc/apollolake: Set up GPIO_TIER1_SCI_EN properlyShaunak Saha
Currently we are setting the gpio_tier1_sci in smihandler before going to S3. But this won't work for S0iX as it happens from Linux kernel and SMI handler is not involved in that flow. We need to set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux kernel before going to sleep checks what values are passed through ASL as wake events (through _PRW), keeps those enabled only and clears other bits in gpe0 enable registers. So we need to inform the kernel to keep gpio_tier_sci also set as these are needed for any wake event. This patch adds ASL code for sleep button device with HID id PNP0C0E. We are adding _PRW method for sleep button device with this patch. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16564 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-15driver/intel/fsp20: move lb_framebuffer functionNaresh G Solanki
move lb_framebuffer function in soc/intel/apollolake to driver/intel/fsp20 so that fsp 2.0 bases soc's can use common lb_framebuffer function. Change-Id: If11bc7faa378a39cf7d4487f9095465a4df84853 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16549 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-14soc/intel/apollolake: Update PL1 value in RAPL MMIO registerSumeet Pawnikar
Due to an incorrect value set for the power limit PL1, the system is not able to leverage full TDP capacity. FSP code sets the PL1 value as 6W in RAPL MMIO register based on fused soc tdp value. This RAPL MMIO register is a physically separate instance from RAPL MSR register. This patch sets PL1 value to 15W in RAPL MMIO register. BUG=chrome-os-partner:56524 TEST=Built, booted on reef and verifed the package power with heavy workload. Change-Id: Ib344247cd8d98ccce7c403e778cd87c13f168ce0 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/16595 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14soc/intel/apollolake: Add PM methods to power gate PCIeVaibhav Shankar
This implements GNVS variable to store the address of PERST_0, _ON/_OFF methods to power gate PCIe during S0ix entry, and PERST_0 assertion/de-assertion methods. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-14soc/intel/apollolake: initialize GNVS structure to 0Aaron Durbin
The code was not previously initializing the GNVS structure to all 0's in the ACPI write tables path. Fix this and also rearrange the ordering of updating the fields to only handle the chip_info specific bits till last such that most of the structure is filled in prior to bailing out in the case of a bad devicetree. Change-Id: I7bdb305c6b87dac96af35b0c3b7524a17ce53962 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16597 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-09soc/intel/apollolake: Add functions to calculate GPIO addressVaibhav Shankar
Provide iosf and GPIO functions for GPIO address calculation. BUG=chrome-os-partner:55877 Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16349 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07soc/apollolake: Enable/disable Audio clk and power gate in devicetree.cbVenkateswarlu Vinjamuri
BUG=chrome-os-partner:56034 Change-Id: Id88d262b32dea468536575117fc34d52076a3096 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16423 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-06google/reef: Enable 20K pull ups for LPC CLKRUN and LAD0:3 linesShamile Khan
The pull up for CLKRUN is required to resolve keyboard slowness and malfunctioning observed on some reef systems. The CLKRUN signal was probed and found to be floating when the pull up was not enabled. Also Added pull ups for the LPC Multiplexed command, address and data lines LAD0:3 because the LPC Interface specification requires them. BUG=chrome-os-partner:55586 BRANCH=none TEST=When a key is pressed, the character is immediately visible on the screen. Also the interrupt count for i8042 increments immediately in /proc/interrupts. Change-Id: I16df1a0301a3994c926a609f61291761219f9e01 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/16426 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-02apollolake: relocate fsp header files to vendorcodeBrandon Breitenstein
FSP header files should be located in vendorcode, not soc directory. This patch includes changes any references to the old location to the new location. Change-Id: I44270392617418ec1b9dec15ee187863f2503341 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16310 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02drivers/intel/fsp2_0: Make FSP Headers Consumable out of BoxBrandon Breitenstein
The following patch is based off of the UEFI 2.6 patch. The FSP header files are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated since the other headers expect it to be in the root of an includable directory. Any struct defines were removed since they are defined in the headers and no longer need to be explicity declared as struct with the UEFI 2.6 includes. BUG=chrome-os-partner:54100 BRANCH=none TEST=confirmed coreboot builds successfully Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com># Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02Fix newlines at the end of filesMartin Roth
All but ga-g41m-es2l/cmos.default had multiple final newlines. ga-g41m-es2l/cmos.default had no final newline. Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16361 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-09-01soc/intel/apollolake: Use consistent convention for community namesFurquan Shaikh
Instead of using a mix of _N and _NORTH, _NW and _NORTHWEST for GPIO community names, follow one single convention. This allows for re-using macros easily. Change-Id: Icd9cf9ef70d03576d864688cf5d6946124c259c3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16353 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31soc/intel/apollolake: Disable Periodic Retraining per-SKUAndrey Petrov
Certain LPDDR4 models have some HW issues that can be worked around by turning off Periodic Retraining feature in the memory controller. Add option to disable PR per SKU. BUG=chrome-os-partner:55466 TEST=run RMT test, pass Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16320 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-31soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3Brandon Breitenstein
Update FSP Header files to provide UPD for periodic training disable. This is for the SIC 1.1.3/150_11 FSP release. BUG=chrome-os-partner:54100 BRANCH=none TEST=built coreboot image with new headers for reef Change-Id: I2ba11aa3d2d664c1d34e39c4c8144fb1c4f2149a Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16352 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-31soc/intel/apollolake: Gather microcode revisionJohn Zhao
Expose get_microcode_info in cpu initialization. Microcode revision is retrieved and stored into log file at verstage. BUG=chrome-os-partner:56544 BRANCH=None TEST=Built coreboot image and validate log file Change-Id: I1e792e70f1318df64b4b85a319700013f3757952 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/16311 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-30soc/intel/apollolake: add option for SLP_S3_L assertion widthAaron Durbin
In order to provide time for the S0 rails to discharge one needs to be able to set the SLP_S3_L assertion width. The hardware default is 60 microcseconds which is not slow enough on most boards. Therefore provide a devicetree option for the mainboard to set accordingly for its needs. An unset value in devicetree results in a conservative 2 second SLP_S3_L duration. BUG=chrome-os-partner:56581 Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16326 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-28soc/intel/apollolake: Add CQOS CAR implementationAndrey Petrov
Add new option to set up Cache-As-RAM by using CQOS, Cache Quality of Service. CQOS allows setting ways of cache in no-fill mode, while keeping other ways in regular evicting mode. This effectively allows using CAR and cache simultaneously. BUG=chrome-os-partner:51959 TEST=switch from NEM to CQOS and back, boot Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15455 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-28soc/intel/apollolake: Update stage link addresses for 768 KiB cacheAndrey Petrov
Update link addresses for romstage and verstage. Also update FSP-M relocation address. BUG=chrome-os-partner:51959 Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15454 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-28soc/intel/apollolake: Handle CAR sizes other than 1 MiBAndrey Petrov
Since whole L2 (1MiB) is not used, it is possible to shrink CAR size to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to set it up. This is a part of CQOS enabling. BUG=chrome-os-partner:51959 Change-Id: I56326a1790df202a0e428e092dd90286c58763c5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15453 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-28src/soc: Remove unnecessary whitespace before "\n" and "\t"Elyes HAOUAS
Change-Id: I89bc8b26f2dba4770aea14b8bbc7e657355e8c59 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16325 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-25soc/intel/apollolake: Enable ELOGBrandon Breitenstein
Add in the base for ELOG for APL. Some PM events still need to be added but the basic events are logged here. This enables the basic functionality of ELOG for Apollolake. BUG=chrome-os-partner:55473 BRANCH=none TEST=Verified image boots on Amenia Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15937 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-25intel/apollolake: Add power management utility functionShaunak Saha
This patch adds a power management utility function to clear wake status bits in ACPI GPE0 registers. We need to call this function before going to sleep from common smi handler function. BUG=chrome-os-partner:55583 BRANCH=None TEST=Verified that system goes to sleep on lidclose and powerd_dbus_suspend command issued from built-in keyboard. Change-Id: Icd095d377c82f2e154f2e2db773f737aa49cda64 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16298 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-24soc/intel/apollolake: Add ASL methods for eMMCVaibhav Shankar
Implement PS0 and PS3 methods to support eMMC power gate in S0ix suspend and resume. BUG=chrome-os-partner:53876 TEST=Suspend and Resume using 'echo freeze > /sys/power/state'. System should resume from S0ix. Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16233 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-23soc/intel/apollolake: Use CONFIG_NHLT_DMIC_2CH_16B for dmicSaurabh Satija
Update the config variable that gets set to use DMIC 2 channel blob for intel/apollolake platforms. This flag is set in mainboard. Change-Id: Ic6deb9f08d345cc45351d61a7597bc7075ee20f9 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/16251 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-20intel/apollolake: Do not halt in poweroff if in SMMFurquan Shaikh
Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered preventing the system from entering sleep state. Fix this by calling halt only if ENV_SMM is not true. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified lidclose behavior on reef. Change-Id: If116c8f4e867543abdc2ff235457c167b5073767 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16257 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-20intel/apollolake: Fix typo in gpi_status_getFurquan Shaikh
sts_index is calculated incorrectly because of wrong use of parenthesis. This lead to wrong bit being checked for EC_SMI_GPI on reef and lidclose event was missed. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified that lidclose event is seen and handled by SMM in coreboot on reef. Change-Id: I56be4aaf30e2d6712fc597b941206ca59ffaa915 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16256 Tested-by: build bot (Jenkins) Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-20soc/intel/apollolake: Save DIMM info from SMBIOS memory HOBRavi Sarawadi
Read FSP produced memory HOB and use it to populate DIMM info. DIMM 'part_num' info is stored statically based on memory/SKU id. BUG=chrome-os-partner:55505 TEST='dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: Ifcbb3329fd4414bba90eb584e065b1cb7f120e73 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/16246 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-19soc/intel/apollolake: use SPI flash boot_device_rw() for ealy stagesAaron Durbin
If the boot device is SPI flash use the common one in the early stages. While tweaking the config don't auto select SPI_FLASH as that is handled automatically by the rest of the build system. BUG=chrome-os-partner:56151 Change-Id: If5e3d06008d5529dd6d7c05d374a81ba172d58fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16201 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19soc/intel/apollolake: make SPI support early stagesAaron Durbin
Using malloc() in SPI code is unnecessary as there's only one SPI device that the SoC support code handles: boot device. Therefore, use CAR to for the storage to work around the current limiations of the SPI API which expects one to return pointers to objects that are writable. BUG=chrome-os-partner:56151 Change-Id: If4f5484e27d68b2dd1b17a281cf0b760086850a7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16195 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19Kconfig: introduce writable boot device notionAaron Durbin
Indicate to the build system that a platform provides support for a writable boot device. The following will provide the necessary support: COMMON_CBFS_SPI_WRAPPER users soc/intel/apollolake soc/intel/baytrail soc/intel/braswell soc/intel/broadwell soc/intel/skylake The SPI_FLASH option is auto-selected if the platform provides write supoprt for the boot device and SPI flash is the boot device. Other platforms may provide similar support, but they do that in a device specific manner such as selecting SPI_FLASH explicitly. This provides clearance against build failures where chipsets don't provide SPI API implementations even though the platform may use a SPI flash to boot. BUG=chrome-os-partner:56151 Change-Id: If78160f231c8312a313f9b9753607d044345d274 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16211 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19Kconfig: separate memory mapped boot device from SPIAaron Durbin
Make the indication of the boot device being memory mapped separate from SPI. However, retain the same defaults that previously existed. BUG=chrome-os-partner:56151 Change-Id: I06f138078c47a1e4b4b3edbdbf662f171e11c9d4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16228 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19intel/apollolake: Skip ITSS configuration in SMMFurquan Shaikh
In SMM, gpio configuration could be done to avoid leakage. ITSS configuration is not required when entering sleep. Thus, bail out early from itss configuration if in SMM. BUG=chrome-os-partner:56281 Change-Id: I4d8be0513aa202f001f980bb91986b50b8ed2a5b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16242 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-18intel/apollolake: Fix check for return value of pmc_gpe_route_to_gpioFurquan Shaikh
pmc_gpe_route_to_gpio returns -1 on error. However, the value was being stored in unsigned int and compared against -1. Fix this by using local variable ret. Change-Id: I5ec824949d4ee0fbdbb2ffdc9fc9d4762455b27b Reported-by: Coverity ID 1357443, 1357442, 1357441 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16218 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-15Revert "Kconfig: separate memory mapped boot device from SPI"Aaron Durbin
This reverts commit a83bbf58541cf41ea7a97dedbc8c02dffa59e86d. This was submitted out of order. Change-Id: Ic5a28faf94c1f1901a72e46343722eb4224c5086 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16226 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-08-15soc/intel/apollolake: don't include all SPI flash driversAaron Durbin
The SPI host controller for the SPI boot device doesn't allow normal probing because it uses the hardware sequencer all the time. Therefore, it's pointless to include unnecessary SPI flash drivers. BUG=chrome-os-partner:56151 Change-Id: I04551fdb0b207c7ec2f1f171cff62ed7334a5ad5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16188 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-15Kconfig: separate memory mapped boot device from SPIAaron Durbin
Make the indication of the boot device being memory mapped separate from SPI. However, retain the same defaults that previously existed. BUG=chrome-os-partner:56151 Change-Id: Ibdd7c8754f9bf560a878136b1f55238e2c2549d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16193 Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-11soc/apollolake: enable access to RTC NVRAMRavi Sarawadi
FSP unconditionally locks parts of the NVRAM in the RTC. This change will enable coreboot to update the locking policy and be able to unlock the region BUG=chrome-os-partner:55944 TEST=Check 'crossystem dev_boot_usb=1' Change-Id: I70fd2bafa6ff9eb9cdf284b9780e4b90dee0f4ce Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/16144 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-10soc/apollolake: add GPIO SMI supportShaunak Saha
GPIOs which trigger SMIs set the GPIO_SMI_STS status bits in SMI_STS register. This patch also sets the SMI_EN bit in enable register for each community based on GPIOROUTSMI bit in gpio pad. When SMI on a gpio happens status needs to be gathered on gpio number which is done by reading the GPI_SMI_STS and GPI_SMI_EN registers. BUG=chrome-os-partner:54977 TEST=When system is in firmware mode executing the command lidclose from ec console shuts down the system. Change-Id: Id89a526106d1989c2bd3416ab81913e6cf743d17 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15833 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-08chromeos chipsets: select RTC usageAaron Durbin
Since RTC is now a Kconfig ensure RTC is selected on the x86 chipsets which are in Chrome OS devices. This allows the eventlog to have proper timestamps instead of all zeros. BUG=chrome-os-partner:55993 Change-Id: I24ae7d9b3bf43a5791d4dc04aae018ce17fda72b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16086 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-04soc/apollolake: Return correct wake status in _SWSShaunak Saha
Wake status is calculated from the four pairs of gpe0 in cbmem CBMEM_ID_POWER_STATE which is filled very early in romstage and depends on the routing information in PMC GPE_CFG register. Coreboot sets the proper value of routing based on devicetree from pmc_init. But when system goes to S3 on waking up PMC is writing default values again in GPE_CFG which results in returning wrong wake status in _SWS. This patch corrects that behaviour by correcting the gpe0 pairs in cbmem after PMC sets the routing table in resume path. BUG=chrome-os-partner:54876 TEST=On resume through powerbtn, lidopen, keyboard press, etc. we are getting proper wake status. Change-Id: I5942d5c20d8c6aef73468dc611190bb7c49c7c7a Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16040 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
2016-08-04soc/intel/apollolake: Configure gpio ownershipJagadish Krishnamoorthy
For the gpio based irq to work, the ownership of the pad should be changed to GPIO_DRIVER. Provide an option in the gpio defs to configure the PAD onwership. BUG=chrome-os-partner:54371 TEST=none Change-Id: I26d242d25d2034049340adf526045308fcdebbc0 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-03drivers/intel/fsp2_0: Handle FspNotify callsLee Leahy
Other SOC platforms need to handle the FspNotify calls in the same way as Apollo Lake. Migrate the FspNotify calls into the FSP 2.0 driver. Provide a platform callback to handle anything else that needs to be done after the FspNotify call. Display the MTRRs before the first call to fsp_notify. TEST=Build and run on Galileo Gen2 Change-Id: I1ff327d77516d4ea212740c16c2514c2908758a2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15855 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: FSP driver handles all FSP errorsLee Leahy
Move all FSP error handling into the FSP 2.0 driver. This removes the need to implement error handling within the SOC code. TEST=Build and run on Galileo Gen2 Change-Id: I4d548b4c90d369d3857c24f50f93e7db7e9d3028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15853 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02google/reef: Add pull up 20K for LPC SERIRQKane Chen
per hw team's check and info from EDS, this pin needs to be pu 20K. Otherwise SoC may not notice interrupt request from EC over LPC because SERIRQ line is floating. BUG=chrome-os-partner:55586 BRANCH=none TEST=boot ok and Quanta factory verified the keyboard issue is gone Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a Reviewed-on: https://review.coreboot.org/15951 Tested-by: build bot (Jenkins) Reviewed-by: Freddy Paul <freddy.paul@intel.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-02soc/intel/apollolake: Add iosstate macros for GPIOShankar, Vaibhav
IO Standby State (IOSSTATE): The I/O Standby State defines which state the pad should be parked in when the I/O is in a standby state. Iosstate set to 15 means IO-Standby is ignored for this pin (same as functional mode), So that pin keeps on functioning in S3/S0iX. Change-Id: Ie51ff86a2ea63fa6535407fcc2df7a137ee43e8b Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/15776 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02intel/apollolake: Enable upper CMOS bank in bootblockFurquan Shaikh
Upper CMOS bank is used to store the boot count. It is important to enable it as soon as possible in bootblock. BUG=chrome-os-partner:55473 Change-Id: I7c4f49c337c2e24a93c1e71466e2f66db04be562 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15998 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31src/soc: Capitalize CPU, ACPI, RAM and ROMElyes HAOUAS
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-30chromeos mainboards: remove chromeos.aslAaron Durbin
Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-30soc/intel/apollolake: Include gpe.h in chip.hFurquan Shaikh
This is required for using GPE_* macros in devicetree.cb. BUG=chrome-os-partner:55670 Change-Id: I8f6f536df96cf8145bb0c03ec413fb2f374301b5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15946 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-29soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resumeAbhay Kumar
Do not pass VBT table to fsp in normal mode and S3 resume so that PEIM GFX will not get initialized. Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/14575 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-28soc/intel/apollolake: Update FSP Header files for version 146_30Brandon Breitenstein
Add new UPDs for Fspm and Fsps. Update headers to make new UPDs available for use. New UPDs enable various memory and trace funtionality options as well as support for zero sized IBB region. BUG=chrome-os-partner:55513 BRANCH=none TEST=built and tested with no regressions Change-Id: Id1573baaa306ed4fe4353df5f27e5963cb1a76e6 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15815 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-28intel/apollolake: Update gnvs for dptfShaunak Saha
This patch updates dptf variable in gnvs based on device configuration by reading the device tree structure. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Amenia and Reef board. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I8ab34cdc94d8cdc840b02347569a9f07688e92cd Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15620 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28intel/apollolake: Add soc specific DPTF valuesShaunak Saha
This patch adds apollolake soc specific change. DPTF ASL files are now in src/soc/intel/common so that they can be reused but different soc can have different values e.g., for skylake cpu soc thermal reporting device is at Bus 0, Device 4, Function 0 while for apollolake it is Bus 0, Device 0, Function 1. This patch adds a dptf asl file in soc directory where we can define all values which can change across soc's and can be included in mainboard dptf asl. BUG=chrome-os-partner:53096 TEST=In Amenia and Reef board verify that the thermal zones are enumerated under /sys/class/thermal in Amenia and Reef board. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I888260a9c799d36512411a769f26dd30cf8d5788 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15619 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28vboot: Separate vboot from chromeosFurquan Shaikh
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use of verified boot library without having to stick to CHROMEOS. BUG=chrome-os-partner:55639 Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15867 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-27soc/intel/apollolake: Disable monitor mwaitBora Guvendik
The monitor/mwait is broken on Apollolake. So use ACPI legacy mwait IO redirection as a work around BUG=chrome-os-partner:55110 Change-Id: I2e1834130d9586b4310466d3549d19bf427ffe24 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/15890 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-25intel/apollolake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOTFurquan Shaikh
This allows the board to save the recovery request in case of unexpected reboots caused by FSP. BUG=chrome-os-partner:55431 Change-Id: If71802d2cba52a426f4c2db90d6c5384ed03ce68 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15803 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-25apollolake: Move CHROMEOS config to SoCFurquan Shaikh
All the mainboards share the same config options for CHROMEOS. Instead of duplicating those in every mainboard, move the CHROMEOS config to SoC and make it dependent on MAINBOARD_HAS_CHROMEOS. BUG=chrome-os-partner:55431 Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15821 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-24soc/intel/apollolake: ensure usb port 0 is in host modeAaron Durbin
The controller for device mode USB is not plan of record on apollolake. However, one still needs to configure the one port to be host mode by default such that the devices work as expected when plugged into the board. BUG=chrome-os-partner:54581,chrome-os-partner:54656 TEST=Enabled xdci controller. Used USB type C->A dongle to check that a mass storage device worked on port 0 on reef. Change-Id: Ia9ec5076491f31bc5dc3d534e235fb49f7b2efac Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15781 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22soc/intel/apollolake: Correct the gpio bank irqJagadish Krishnamoorthy
The gpio bank irq is not correct and hence gpio bank handler is never called in case of gpio based irq. Correct the gpio bank irq to enable gpio based irq. BUG=chrome-os-partner:55433 TEST=cat /proc/interrupts | grep INT3452 should output 14. Change-Id: I54253786425b7d4c2007043d49a91dfa6db0397b Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15756 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-22soc/intel/apollolake: clarify meaning of LPDDR4 density meaningAaron Durbin
The 'dram density' is a misnomer because the memory initialization code treats that input parameter as a per rank density. Therefore, update the variables to further clarify how it's actually being used. BUG=chrome-os-partner:55446 Change-Id: Ie4c944f35b531812205ac0bb1c70f39ac401495e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15773 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22soc/intel/apollolake: add dual rank option to meminitAaron Durbin
Despite the UPD comments the Chx_RankEnable fields are a bit mask which indicates which ranks are enabled for physical channel. Add the ability to set the rank mask correctly for dual rank LPDDR4 modules. BUG=chrome-os-partner:55446 Change-Id: I9dbed7bb6a4b512e57f6b4481180932a7cce91ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15771 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22soc/intel/apollolake: die() when FSP silicon init failsAaron Durbin
The reset requests are handled in the FSP 2.0 wrapper, but the current code doesn't check any non-successful return values. Provide parity with the memory init path which die()s under those circumstances. Change-Id: I9df61323f742b4e94294321e3ca3ab58a68ca4dd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15766 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21soc/intel/apollolake: Add new Intel HD Graphics Device ID's.Abhay Kumar
B stepping onwards we have to support two Graphics Device ID. BUG=chrome-os-partner:55449 Change-Id: I520791ad8573dc5deb6ea1e33e1486f05050438c Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/15767 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-19drivers/intel/fsp2_0: Split reset handling logicAndrey Petrov
FSP 2.0 spec only defines 2 reset request (COLD, WARM) exit codes. The rest 6 codes are platform-specific and may vary. Modify helper function so that only basic resets are handled and let SoC deal with the rest. Change-Id: Ib2f446e0449301407b135933a2088bcffc3ac32a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15730 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-19soc/intel/apollolake: Implement reset_prepare()Andrey Petrov
At first boot CSE spends long time preparing media for use. As result it may not be able to deal with a CPU reset. Add reset_prepare() callback that polls CSE readiness. BUG=chrome-os-partner:55055 TEST=build with release version of fsp, reboot, observe polling for CSE, then proper reboot happening Change-Id: I639ef900b97132f1a7f269bb864d70009df9fdfe Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15721 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19soc/intel/apollolake: Add basic HECI supportAndrey Petrov
Add functions to read Host Firmware Status register and a helper function to determine if CSE is ready. BUG=chrome-os-partner:55055 TEST=none Change-Id: If511a51c04f7e59427d7952fa67b61060e2be404 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15713 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19drivers/intel/fsp2_0: load and relocate FSPS in cbmemAaron Durbin
The FSPS component loading was just loading to any memory address listed in the header. That could be anywhere in the address space including ramstage itself -- let alone corrupting the OS memory on S3 resume. Remedy this by loading and relocating FSPS into cbmem. The UEFI 2.4 header files include path are selected to provide the types necessary for FSP relocation. BUG=chrome-os-partner:52679 Change-Id: Iaba103190731fc229566a3b0231cf967522040db Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15742 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: John Zhao <john.zhao@intel.com>
2016-07-19drivers/intel/fsp2_0: handle XIP and non-XIP for FSPM componentAaron Durbin
The previously implementation for loading the FSPM component didn't handle platforms which expects FSPM to be XIP. For the non-XIP case, romstage's address space wasn't fully being checked for overlaps. Lastly, fixup the API as the range_entry isn't needed any longer. This API change requires a apollolake to be updated as well. BUG=chrome-os-partner:52679 Change-Id: I24d0c7d123d12f15a8477e1025bf0901e2d702e7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15741 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: implement common memory_init() tasksAaron Durbin
Instead of performing the same tasks in the chipset code move the common sequences into the FSP 2.0 driver. This handles the S3 paths as well as saving and restoring the memory data. The chipset code can always override the settings if needed. BUG=chrome-os-partner:52679 Change-Id: I098bf95139a0360f028a50aa50d16d264bede386 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15739 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: set BootLoaderTolumSize genericallyAaron Durbin
The amount of reserved memory just below the DRAM limit in 32-bit space is defined in the FSP 2.0 specification within the FSPM_ARCH_UPD structure. There's no need to make the chipset code set the same value as needed for coreboot. The chipset code can always change the value if it needs after the common setting being applied. Remove the call in soc/intel/apollolake as it's no longer needed. BUG=chrome-os-partner:52679 Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19soc/intel/apollolake: remove unused FIT_POINTER defineAaron Durbin
Change-Id: I97be4f8cecbf9cf2adda2e0c1650e03acd7eb1cb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15736 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19soc/intel/apollolake: Fix bitshift issue in bootblockAndrey Petrov
Fix issue where zero-sized BIOS region could cause bitshift for '-1' which is an unspecified behavior. Change-Id: Icb62bf413a1a0d293657503ef21fe97b5f9a5484 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15727 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15soc/intel/apollolake: Consolidate ISH enablingAndrey Petrov
Since the Integrated Sensor Hub can be disabled through devicetree.cb as a PCI device, there is no need for a separate register variable. Remove handling the register and update mainboards' devicetrees. Also keep ISH disabled on both Reef and Amenia. Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15710 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/apollolake: Properly disable PCIe root portsKane Chen
1. The hotplug feature needs to be disabled so that pcie root ports will be disabled by fsp 2. Correct PcieRootPortEn mapping. The correct mapping should be like below PcieRootPortEn[0] ==> 00:14.0 PcieRootPortEn[1] ==> 00:14.1 PcieRootPortEn[2] ==> 00:13.0 PcieRootPortEn[3] ==> 00:13.1 PcieRootPortEn[4] ==> 00:13.2 PcieRootPortEn[5] ==> 00:13.3 BUG=chrome-os-partner:54288 BRANCH=None TEST=Checked pcie root port is disabled properly and make sure pcie ports are coalesced. Also make sure the device will still be enabled after coalescence when pcie on function 0 is disabled devicetree Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/15595 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 10:08:43 +0000