coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-12-07	soc/intel/apollolake: Clean up UART code	Aamir Bohra
	Clean up and move UART related code under a single uart.c file. Change-Id: I9a30258ba43ee5920f585c1bd06bc25773778ec4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-10	soc/intel/apollolake: Enable UART debug controller on S3 resume	Furquan Shaikh
	1. Add a new variable to GNVS to store information during S3 suspend whether UART debug controller is enabled. 2. On resume, read stored GNVS variable to decide if UART debug port controller needs to be initialized. 3. Provide helper functions required by intel/common UARRT driver for enabling controller on S3 resume. BUG=b:64030366 Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20888 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-09	soc/intel/apollolake: Use common/block/uart code	Aamir Bohra
	Change-Id: I92c654d59f1642bcd7c95de80dcc641bf816b542 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28	soc/pci_devs.h: Use consistent naming in soc/pci_devs.h	Subrata Banik
	This patch to make common PCI device name between APL and SKL. Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-12	soc/apollolake/uart.c: Do not NOOP .set_resources() and friends	Alexandru Gagniuc
	When SOC_UART_DEBUG was not set, the boot would hang somwhere in ramstage, as evidenced by POST codes reported from the EC. This was traced to the .set_resources and .enable_resources members of the UART PCI driver being set to NOOP. Although the exact mechanism of failure is not known, this change eliminates the hang. Change-Id: Ic2f3d56a964ec890ebfa1e1a7770f1ae2eb22281 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14771 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-14	soc/intel: Update license headers	Martin Roth
	Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-10	soc/intel/apollolake: Avoid UART BAR relocation at ramstage	Andrey Petrov
	UART bar gets overwritten during resource allocation stage. As result the serial driver ends up using stale BAR so serial output does not work. This driver simply tells resource allocator not to change BAR of UART device. Change-Id: I81f4f04089106c80bea97f0bbaba890df00c8ac5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13997 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)