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When SOC_UART_DEBUG was not set, the boot would hang somwhere in
ramstage, as evidenced by POST codes reported from the EC. This was
traced to the .set_resources and .enable_resources members of the UART
PCI driver being set to NOOP.
Although the exact mechanism of failure is not known, this change
eliminates the hang.
Change-Id: Ic2f3d56a964ec890ebfa1e1a7770f1ae2eb22281
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14771
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14321
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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UART bar gets overwritten during resource allocation stage. As result
the serial driver ends up using stale BAR so serial output does not
work. This driver simply tells resource allocator not to change BAR
of UART device.
Change-Id: I81f4f04089106c80bea97f0bbaba890df00c8ac5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13997
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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