coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-06-09	soc/intel/apollolake: Use CPU common library code	Barnali Sarkar
	This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I529c67cf20253cf819d1c13849300788104b083c Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-05	soc/intel/apollolake: Use Intel timer common code	Aamir Bohra
	Change-Id: I7b415711d01ddc0d998eba62de2c2139045efa80 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-05	soc/intel/apollolake: Add config for cpu base clock frequency	Aamir Bohra
	Add config for cpu base clock frequency(Mhz), use and clean up code. Change-Id: I724c48c11796aa942295d4f19cc629d4c13647e1 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/20017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-13	soc/intel/apollolake: Fix issues detected by checkpatch	Lee Leahy
	Fix the following errors and warnings detected by checkpatch.pl: ERROR: switch and case should be at the same indent ERROR: do not use assignment in if condition WARNING: Statements terminations use 1 semicolon WARNING: unnecessary whitespace before a quoted newline WARNING: else is not generally useful after a break or return TEST=Build for reef Change-Id: I5486936dbf19b066c76179d929660affa1da5f16 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18727 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/apollolake: Indent code using tabs	Lee Leahy
	Fix the following error and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs TEST=Build for reef Change-Id: Id7a758463b95274c5e8bbdd67da0955f1ae78aac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18721 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-14	intel/apollolake: Enable turbo	Shaunak Saha
	This patch adds punit initialization code after FspMemoryInit so that turbo can be initialized after that. BUG=chrome-os-partner:58158 BRANCH=None Change-Id: I4939da47da82b9a728cf1b5cf6d5ec54b4f5b31d Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/17203 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-14	soc/intel: Update license headers	Martin Roth
	Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-11	soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE	Andrey Petrov
	Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>