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path: root/src/soc/intel/apollolake/spi.c
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2016-12-07soc/intel/apollolake: Use the new SPI driver interfaceFurquan Shaikh
1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully for reef. Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17562 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-06spi_flash: Make a deep copy of spi_slave structureFurquan Shaikh
Commit 36b81af (spi: Pass pointer to spi_slave structure in spi_setup_slave) changes the way spi_setup_slave handles the spi_slave structure. Instead of expecting spi controller drivers to maintain spi_slave structure in CAR_GLOBAL/data section, caller is expected to manage the spi_slave structure. This requires that spi_flash drivers maintain spi_slave structure and flash probe function needs to make a copy of the passed in spi_slave structure. This change fixes the regression on Lenovo X230 and other mainboards. Change-Id: I0ad971eecaf3bfe301e9f95badc043193cc27cab Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17728 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Iru Cai <mytbk920423@gmail.com>
2016-12-05spi: Define and use spi_ctrlr structureFurquan Shaikh
1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17684 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Pass pointer to spi_slave structure in spi_setup_slaveFurquan Shaikh
For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Fix parameter types for spi functionsFurquan Shaikh
1. Use size_t instead of unsigned int for bytes_out and bytes_in. 2. Use const attribute for spi_slave structure passed into xfer, claim bus and release bus functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22soc/intel: Use correct terminology for SPI flash operationsFurquan Shaikh
FPR is an attribute of the SPI flash component and not of the SPI bus itself. Rename functions, file names and Kconfig option to make sure this is conveyed correctly. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: I9f06f1a8ee28b8c56db64ddd6a19dd9179c54f50 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17560 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22spi: Get rid of flash_programmer_probe in spi_slave structureFurquan Shaikh
flash_programmer_probe is a property of the spi flash driver and does not belong in the spi_slave structure. Thus, make spi_flash_programmer_probe a callback from the spi_flash_probe function. Logic still remains the same as before (order matters): 1. Try spi_flash_programmer_probe without force option 2. Try generic flash probing 3. Try spi_flash_programmer_probe with force option If none of the above steps work, fail probing. Flash controller is expected to honor force option to decide whether to perform specialized probing or to defer to generic probing. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I4163593eea034fa044ec2216e56d0ea3fbc86c7d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-15intel/apollolake: Ensure SPI operations do not cross 256-byte boundaryFurquan Shaikh
BIOS needs to ensure that SPI write does not cross 256-byte boundary. Else, if the write is across 256-byte boundary, then it corrupts the block by wrapping write to start of current block. Thus, ensure nuclear_spi_{read,write} operate within a single 256-byte block only at a time. BUG=chrome-os-partner:59813 BRANCH=None TEST=Verified that elog writes do not corrupt the event log when write is across 256-byte blocks. Change-Id: I854ca2979d65b9f1232f93182cb84d4dee4f4139 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-03soc/intel/apollolake: Implement SPI flash status register readFurquan Shaikh
This was a dummy implementation until now which returned -1 always. Add support for reading SPI flash status register (srp0). BUG=chrome-os-partner:59267 BRANCH=None TEST=Verified by enabling and disabling write-protect on reef that the value of SRP0 changes accordingly in status register read. Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17205 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-26soc/intel/apollolake: Enable write-protect SPI flash range supportFurquan Shaikh
Use intel common infrastructure to enable support for write-protecting SPI flash range. Also, enable this protection for RW_MRC_CACHE. BUG=chrome-os-partner:58896 TEST=Verified that write to RW_MRC_CACHE fails in OS using "flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin" Change-Id: I35df12bc295d141e314ec2cb092d904842432394 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17117 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-19soc/intel/apollolake: make SPI support early stagesAaron Durbin
Using malloc() in SPI code is unnecessary as there's only one SPI device that the SoC support code handles: boot device. Therefore, use CAR to for the storage to work around the current limiations of the SPI API which expects one to return pointers to objects that are writable. BUG=chrome-os-partner:56151 Change-Id: If4f5484e27d68b2dd1b17a281cf0b760086850a7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16195 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23intel/apollolake: Enable prefetching and caching for BIOS readsFurquan Shaikh
Change-Id: I6afcc17ec8511d3fd4c1ac3b15d523d9b6752120 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15321 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-21intel/apollolake: Add helper routine for spi reg readFurquan Shaikh
BUG=chrome-os-partner:54563 Change-Id: I56bc6b5292aec676103a436048abee8577edd961 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15268 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/apollolake: Rename _spi_reg_read/write to _spi_ctrlr_read/writeFurquan Shaikh
This makes it clearer that the read/write operations are being performed on the host controllers registers. Change-Id: Id63d778a4a03c461d97e535c34b85ada3ae469de Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15281 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/apollolake/spi: Add support for reading status regFurquan Shaikh
spi_read_status reads the status register using hardware sequencing and returns 0 on success and -1 on error. Use spi_read_status to return appropriate value for get_sw_write_protect. BUG=chrome-os-partner:54283 Change-Id: I7650b5c0ab05a8429c2b291f00d4672446d86e03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15266 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-14soc/intel: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-11soc/intel/apollolake: Implement SPI controller driverAlexandru Gagniuc
Implement flash read, write, and erase functionality using the hardware sequencing capabilities of the SOC. Due to changes in hardware requirements, the flash chip must be probed differently than on previous platforms (details explained in comments). Note that this is a minimal implementation, and does not provide all the bells and whistles. Change-Id: I6dcc3bc36dfce61927d126d231a16d485acb1bdc Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14246 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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