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2017-08-08soc/intel/apollolake: Use common PMC for apollolakeShaunak Saha
With this patch apollolake uses the common PMC util code.No regression observed on a APL platform. Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/19375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/intel/apollolake: Rename ACPI Base Address and Size MacroBarnali Sarkar
Rename these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20038 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-01soc/intel/apollolake: Remove soc/pci_ids dependencyHannah Williams
and add pci ids for GLK and APL from device/pci_ids.h Change-Id: If8101fe52591b09caadfe104ca8daab4258837c7 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19999 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-16soc/intel/apollolake: clear PMC registersAaron Durbin
The clearing of the PMC registers was not being called resulting in state persisting across reboots. This state is queried and events are added to the eventlog like 'RTC reset' events. However, the RTC reset event is a one time thing so it should only be logged once. Without the clearing of the state the event was logged on every boot. BUG=chrome-os-partner:58496 Change-Id: I60aa7102977c2b1775ab8c54d1c147737d2af5e2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17027 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-28soc/intel/apollolake: Use fixed resource for SRAM and IPC1Lijian Zhao
Intel telemetry support will require PMC IPC1 and SRAM devices to be operated in ACPI mode. Then using fixed resources on BAR0, BAR1 and BAR2 (PMC only) for those two devices will help the resource assignment in DSDT stage. BUG=chrome-os-partner:57364 BRANCH=None TEST=Boot up into Chrome OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/16648 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21soc/intel/apollolake: Initialize GPEs in bootblockDuncan Laurie
Initialize the GPEs from mainboard config in bootblock, so they can be used in verstage to query latched interrupt status. I still left it called in ramstage just to be sure that the configuration was not overwritten in FSP stages. Tested by reading and reporting GPE status in a loop in verstage and manually triggering an interrupt on EC console. BUG=chrome-os-partner:53336 Change-Id: Iacd0483e4b3229aca602bb5bb40586eedf35a6ea Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16670 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19Revert "soc/intel/apollolake: Initialize GPEs in bootblock"Duncan Laurie
This reverts commit 5e3dad66227bba4be9365ee76d00231bb5577b56.
2016-09-19soc/intel/apollolake: Initialize GPEs in bootblockDuncan Laurie
Initialize the GPEs from mainboard config in bootblock, so they can be used in verstage to query latched interrupt status. I still left it called in ramstage just to be sure that the configuration was not overwritten in FSP stages. Tested by reading and reporting GPE status in a loop in verstage and manually triggering an interrupt on EC console. BUG=chrome-os-partner:53336 Change-Id: I1af3e9ac1e5c59b9ebb5c6dd1599309c1f036581 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-30soc/intel/apollolake: add option for SLP_S3_L assertion widthAaron Durbin
In order to provide time for the S0 rails to discharge one needs to be able to set the SLP_S3_L assertion width. The hardware default is 60 microcseconds which is not slow enough on most boards. Therefore provide a devicetree option for the mainboard to set accordingly for its needs. An unset value in devicetree results in a conservative 2 second SLP_S3_L duration. BUG=chrome-os-partner:56581 Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16326 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-25soc/intel/apollolake: Enable ELOGBrandon Breitenstein
Add in the base for ELOG for APL. Some PM events still need to be added but the basic events are logged here. This enables the basic functionality of ELOG for Apollolake. BUG=chrome-os-partner:55473 BRANCH=none TEST=Verified image boots on Amenia Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15937 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-10soc/apollolake: add GPIO SMI supportShaunak Saha
GPIOs which trigger SMIs set the GPIO_SMI_STS status bits in SMI_STS register. This patch also sets the SMI_EN bit in enable register for each community based on GPIOROUTSMI bit in gpio pad. When SMI on a gpio happens status needs to be gathered on gpio number which is done by reading the GPI_SMI_STS and GPI_SMI_EN registers. BUG=chrome-os-partner:54977 TEST=When system is in firmware mode executing the command lidclose from ec console shuts down the system. Change-Id: Id89a526106d1989c2bd3416ab81913e6cf743d17 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15833 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-04soc/apollolake: Return correct wake status in _SWSShaunak Saha
Wake status is calculated from the four pairs of gpe0 in cbmem CBMEM_ID_POWER_STATE which is filled very early in romstage and depends on the routing information in PMC GPE_CFG register. Coreboot sets the proper value of routing based on devicetree from pmc_init. But when system goes to S3 on waking up PMC is writing default values again in GPE_CFG which results in returning wrong wake status in _SWS. This patch corrects that behaviour by correcting the gpe0 pairs in cbmem after PMC sets the routing table in resume path. BUG=chrome-os-partner:54876 TEST=On resume through powerbtn, lidopen, keyboard press, etc. we are getting proper wake status. Change-Id: I5942d5c20d8c6aef73468dc611190bb7c49c7c7a Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16040 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-02soc/intel/apollolake: Add GPE routing codeShaunak Saha
This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-04soc/apollolake/pmc: Store the ACPI bar during set_resources stageAlexandru Gagniuc
Because the resource for the ACPI BAR is fixed, pci_dev_set_resources does not store it to the device. This means we need to do part of the dance to get the ACPI IO region to work after coreboot. Of course, this BAR can be destroyed later by the OS probing it, but at least we try to get it working out of coreboot. Change-Id: Ibff18d30936f94d4f149a89313254531365f43e6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/15048 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-12soc/apollolake: Handle non-standard ACPI BAR in PMC deviceAlexandru Gagniuc
The ACPI BAR (BAR2 - offset 0x20) is not PCI compliant. That means that probing may not work. In that case, a resource still needs to be created for the BAR. BONUS: We now avoid the need to declare the MMIO resources as fixed. Change-Id: I52fd2d2718ac8013067aaa450c5eb31e00738ab9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14634 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-30soc/apollolake: Prevent PMC BAR reassignment during resource allocationHannah Williams
Change-Id: Ie8e21e62ecd25f3c620a57c24948411c14c1e111 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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