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2020-12-08coreboot tables: Add SPI flash memory map windows to coreboot tablesFurquan Shaikh
This change adds details about the memory map windows to translate addresses between SPI flash space and host address space to coreboot tables. This is useful for payloads to setup the translation using the decode windows already known to coreboot. Until now, there was a single decode window at the top of 4G used by all x86 platforms. However, going forward, platforms might support more decode windows and hence in order to avoid duplication in payloads this information is filled in coreboot tables. `lb_spi_flash()` is updated to fill in the details about these windows by making a call to `spi_flash_get_mmap_windows()` which is implemented by the driver providing the boot media mapping device. BUG=b:171534504 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I00ae33d9b53fecd0a8eadd22531fdff8bde9ee94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48185 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08commonlib/region: Allow multiple windows for xlate_region_devFurquan Shaikh
This change updates the translated region device (xlate_region_dev) to support multiple translation windows from the 1st address space to 2nd address space. The address spaces described by the translation windows can be non-contiguous in both spaces. This is required so that newer x86 platforms can describe memory mapping of SPI flash into multiple decode windows in order to support greater than 16MiB of memory mapped space. Since the windows can be non-contiguous, it introduces new restrictions on the region device ops - any operation performed on the translated region device is limited to only 1 window at a time. This restriction is primarily because of the mmap operation. The caller expects that the memory mapped space is contiguous, however, that is not true anymore. Thus, even though the other operations (readat, writeat, eraseat) can be updated to translate into multiple operations one for each access device, all operations across multiple windows are prohibited for the sake of consistency. It is the responsibility of the platform to ensure that any section that is operated on using the translated region device does not span multiple windows in the fmap description. One additional difference in behavior is xlate_region_device does not perform any action in munmap call. This is because it does not keep track of the access device that was used to service the mmap request. Currently, xlate_region_device is used only by memory mapped boot media on the backend. So, not doing unmap is fine. If this needs to be changed in the future, xlate_region_device will have to accept a pre-allocated space from the caller to keep track of all mapping requests. BUG=b:171534504 Change-Id: Id5b21ffca2c8d6a9dfc37a878429aed4a8301651 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47658 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cbfs.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <cbfs.h>' -- src/) <(git grep -l 'cbfs_boot_map_optionrom\|cbfs_boot_map_optionrom_revision\|cbfs_boot_locate\|cbfs_boot_map_with_leak\|cbfs_locate_file_in_region\|cbfs_boot_load_file\|cbfs_load_and_decompress\|cbfs_prog_stage_load\|cbfs_boot_region_device' -- src/) |grep '<' |grep -v vendorcode Also add missing 'include <cbfs.h>' in src/soc/qualcomm/sc7180/qupv3_config.c Change-Id: Icaecb5b910888f34cddedab7b2f64eaf6d01ad66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-18intel/apollolake: Remove CBFS locator overrideJulius Werner
This patch removes the CBFS locator override for the Apollolake SoC and instead integrates the extra sanity check it was used for straight in the boot device initializer. Change-Id: Iccdb885be233bb027a6a1f2cc79054582cbdf3fc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-20cbfs: switch to region_device for location APIsAaron Durbin
Drop struct cbfs_props and replace with struct region_device object. The goal of the cbfs locator APIs are to determine the correct region device to find the cbfs files. Therefore, start directly using struct region_device in the cbfs location paths. Update the users of the API and leverage the default boot region device implementation for apollolake. Change-Id: I0158a095cc64c9900d8738f8ffd45ae4040575ea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-14cbfs: Stop checking master headerJulius Werner
The CBFS master header is a legacy structure that just conveys the same information we already have from the FMAP these days. We're still including it to support older CBFS implementations in some payloads, but there's no need for coreboot itself to follow this indirection anymore. This patch simplifies the default CBFS locator to just return the CBFS offset and size from the FMAP directly. Change-Id: I6b00dd7f276364d62fa1f637efbaee0e80607c49 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36688 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29soc/intel/apollolake: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I0f393385aa94f18c2e05af3b5a54999575323d18 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-12-06soc/intel/apl: Warn if CBFS is outside the memory mapped areaNico Huber
As part of the memory mapped BIOS region is covered by SRAM, check that CBFS always fits the effectively mapped region of flash. This is usually taken care of by reserving the SRAM range in the FMAP (e.g. as BIOS_UNUSABLE), but can be missed. Change-Id: If5a5b553ad4853723bf13349c809c4f6154aa5f2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-05soc/intel/common/block: add bios caching to fast spi moduleAaron Durbin
Add fast_spi_cache_bios_region() that sets up a variable MTRR as write-protect covering the fast spi BIOS region. Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-02soc/intel/apollolake: Clean up code by using common FAST_SPI moduleBarnali Sarkar
This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: Ifd72734dadda541fe4c828e4f1716e532ec69c27 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19080 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-24soc/intel/apollolake: Remove unused CAR_GLOBAL variableSubrata Banik
Also move all local variable declaration at starting of function block. Change-Id: I774485a23b4b7d96a8dbd837da45553251dff3b0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18949 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-13soc/intel/apollolake: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build for reef Change-Id: I4fbe95037ca4b52e64ba37e5c739af4a03f64feb Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18728 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-15soc/intel/common: remove mrc cache assumptionsAaron Durbin
Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-07soc/intel/apollolake: Use the new SPI driver interfaceFurquan Shaikh
1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully for reef. Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17562 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24region: Add writeat and eraseat supportAntonello Dettori
Implement writeat and eraseat support into the region_device_ops struct. Change-Id: Iac2cf32e523d2f19ee9e5feefe1fba8c68982f3d Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15318 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-22intel/apollolake: Add API for get_bios_size and use itFurquan Shaikh
get_bios_size returns the value of bios_size. Use this function to calculate bios_size for caching in bootblock. BUG=chrome-os-partner:54563 Change-Id: I2e592b1c52138bd4623ad2acd05c744224a8e50b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15292 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-21intel/apollolake: Calculate BIOS mmap at runtimeFurquan Shaikh
Instead of hard-coding the BIOS region start and end addresses, read BIOS_BFPREG to determine the base and limit for the mapped BIOS region. BUG=chrome-os-partner:54563 Change-Id: Iddd3d4cc945f09e8f147e293bb9144471a6a220d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15269 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-21commonlib/region: Rename XLATE region device init macroFurquan Shaikh
This makes the name consistent with other region device init macros. Change-Id: I248894ba6c85326b615dcb71e8f498bc8be50911 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15277 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31soc/intel/apollolake: Update SPI memory mapping constraintsAndrey Petrov
MMIO region of 256 KiB under 4 GiB is not decoded by SPI controller by hardware design. Current code incorrectly specifies size of that region to be 128 KiB. This change corrects the value to 256 KiB. Change-Id: Idcc67eb3565b800d835e75c0b765dd49d1656938 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14979 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-14soc/intel: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-08soc/intel/apollolake: Override default to_flash_offset implementationAlexandru Gagniuc
The default nvm_mmio_to_flash_offset() implementation used by NVM code in intel/common does not work on apollolake. As a result, provide the correct override. Change-Id: I01a94f90dfdd33586a4aac5c05dd8c73e8804437 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14248 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08soc/intel/apollolake: Add support for memory-mapped boot mediaAndrey Petrov
On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13706 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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