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path: root/src/soc/intel/apollolake/i2c.c
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2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06soc/intel/apollolake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I3c6daa484a4aa133ff2ad79eb2b8efa159da3523 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-06-06soc/intel/common/block: Move i2c common functions into block/i2cSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/i2c. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: I88f2f836eee4f80b79486dd8644d1bb3826c5af1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-25drivers/i2c/designware: reduce API complication for bus configAaron Durbin
Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement that callback for obtaining the bus config. However, we're currently forcing another parameter of struct device so one can do the lookup. This works for Intel-based systems since the struct device was needed to program the BAR, etc. However, from an API standpoint, it just complicates matters by needing to obtain the struct device. The SoC already has knowlege of its own devices so it can get the config itself by bus number. Therefore, remove that contraint from the API. BUG=b:70232394 Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23420 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24drivers/i2c/designware: namespace soc functionsAaron Durbin
Rename the following functions to ensure it's clear that the designware i2c host controller driver is the one that these functions are associated with: i2c_get_soc_cfg() -> dw_i2c_get_soc_cfg() i2c_get_soc_early_base() -> dw_i2c_get_soc_early_base() i2c_soc_devfn_to_bus() -> dw_i2c_soc_devfn_to_bus() i2c_soc_bus_to_devfn() -> dw_i2c_soc_bus_to_devfn() BUG=b:72121803 Change-Id: Idb7633b45a0bb7cb7433ef5f6b154e28474a7b6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23371 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22ic2/designware: Move Intel i2c logic to shared driverChris Ching
BUG=b:70232394 BRANCH=none TEST=emerge-reef coreboot emerge-glados Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05soc/intel/{common,apollolake}: Add checks to handle negative valuesRizwan Qureshi
Fix issues reported by coverity scan in the below files. src/soc/intel/common/block/i2c 1375440: Improper use of negative value 1375441: Improper use of negative value 1375444: Improper use of negative value src/soc/intel/apollolake/i2c.c 1375442: Unsigned compared against 0 Change-Id: Ic65400c934631e3dcd3aa664c24cb451616e7f4d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-18intel/common/block/i2c: Add common block for I2C and use the same in SoCsRizwan Qureshi
In the intel/common/block * Move I2C common code from intel/common to intel/common/block. * Split the code into common, early init and post mem init stages and put it in lpss_i2c.c, i2c_early.c and i2c.c respectively. * Declare functions for getting platform specific i2c bus config and mapping bus to devfn and vice versa, that have to be implemented by SoC. In skylake/apollolake * Stop using code from soc/intel/common/lpss_i2c.c. * Remove early i2c initialization code from bootblock. * Refactor i2c.c file to implement SoC specific methods required by the I2C IP block. Change-Id: I4d91a04c22e181e3a995112cce6d5f0324130b81 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-13soc/intel/apollolake: Fix unsigned warningsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build for reef Change-Id: Ifc45ce90d466d087cd20af72ddfc8486d2f1492c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18724 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-12soc/intel/common/lpss_i2c: configure buses by rise/fall timesAaron Durbin
The default register count calculations are leading to higher frequencies than expected. Provide an alternative method for calculating the register counts by utilizing the rise and fall times of the bus. If the rise time is supplied the rise/fall time values are used, but the register overrides take precedence over the rise/fall time calculation. This allows platforms to choose whichever method works the best. BUG=chrome-os-partner:58889 Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17350 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-11soc/intel/common/lpss_i2c: simplify API and use common config structureAaron Durbin
The apollolake and skylake had duplicate stanzas of code for initializing the i2c buses. Additionally, they also had very similar structures for providing settings for the i2c speed control. Introduce a new struct lpss_i2c_bus_config and utilize it in both apollolake and skylake thereby removing the need for SoC-specific structres. The new structure is used for initializing a bus fully as the lpss i2c API is simplified in that lpss_i2c_init() is only required to be called. The struct lpss_i2c_bus_config structure is passed in for both initializing and filling in the SSDT information. The formerly exposed functions are made static to reduce the external API exposure. BUG=chrome-os-partner:58889 Change-Id: Ib4fa8a7a4de052da75c778a7658741a5a8e0e6b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17348 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-02soc/intel/apollolake: Add support for LPSS I2C driverDuncan Laurie
Support the I2C interfaces on this SOC using the Intel common lpss_i2c driver. The controllers are supported in pre-ram environments by setting a temporary base address in bootblock and in ramstage using the naturally enumerated base address. The base speed of this controller is 133MHz and the SCL/SDA timing values that are reported to the OS are calculated using that clock. This was tested on a google/reef board doing I2C transactions to the trackpad both in verstage and in ramstage. Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15480 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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