coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2016-08-10	soc/apollolake: add GPIO SMI support	Shaunak Saha
	GPIOs which trigger SMIs set the GPIO_SMI_STS status bits in SMI_STS register. This patch also sets the SMI_EN bit in enable register for each community based on GPIOROUTSMI bit in gpio pad. When SMI on a gpio happens status needs to be gathered on gpio number which is done by reading the GPI_SMI_STS and GPI_SMI_EN registers. BUG=chrome-os-partner:54977 TEST=When system is in firmware mode executing the command lidclose from ec console shuts down the system. Change-Id: Id89a526106d1989c2bd3416ab81913e6cf743d17 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15833 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-04	soc/intel/apollolake: Configure gpio ownership	Jagadish Krishnamoorthy
	For the gpio based irq to work, the ownership of the pad should be changed to GPIO_DRIVER. Provide an option in the gpio defs to configure the PAD onwership. BUG=chrome-os-partner:54371 TEST=none Change-Id: I26d242d25d2034049340adf526045308fcdebbc0 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-02	soc/intel/apollolake: Add iosstate macros for GPIO	Shankar, Vaibhav
	IO Standby State (IOSSTATE): The I/O Standby State defines which state the pad should be parked in when the I/O is in a standby state. Iosstate set to 15 means IO-Standby is ignored for this pin (same as functional mode), So that pin keeps on functioning in S3/S0iX. Change-Id: Ie51ff86a2ea63fa6535407fcc2df7a137ee43e8b Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/15776 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-13	soc/intel/apollolake: set gpio interrupt polarity in ITSS	Aaron Durbin
	For APIC routed gpios, set the corresponding interrupt polarity for the associated IRQ based on the gpio pad's invert setting. This allows for the APIC redirection entries to match the hardware active polarity once the double inversion takes place to meet apollolake interrupt triggering constraints. BUG=chrome-os-partner:54955 Change-Id: I69c395b6f861946d4774a4206cf8f5f721c6f5f4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15648 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07	soc/intel/apollolake: make internal pulls weak for gpio inputs	Aaron Durbin
	The internal pulls for gpio_input_pullup() and gpio_input_pulldown() were using fairly strong pulls. Weaken them so that external pulls can override the internal ones. This matches the current assumptions of lib/gpio.c. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifda1d04d40141325f78db277eb0bd55574994abf Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15558 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-02	soc/intel/apollolake: Add GPE routing code	Shaunak Saha
	This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-02	soc/intel/apollolake: Add function to translate gpio_t into ACPI pin	Duncan Laurie
	There are four GPIO communities in this SOC and they are implemented as separate ACPI devices. This means the pin number that is used in an ACPI GPIO declaration needs to be relative to the community that the pin resides in. Also select GENERIC_GPIO_LIB in the SOC Kconfig so this function actually gets used. This was tested on the reef mainboard by verifying the output of the SSDT for the Maxim 98357A codec that the assigned GPIO_76 is listed as pin 0x24 which is the value relative to the Northwest community. Change-Id: Iad2ab8eccf4c91185a075ffce8d41c81f06c1113 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15513 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-21	apollolake: Add handler for finding ACPI path for GPIO	Duncan Laurie
	Add a handler for soc/intel/apollolake to return the ACPI path for GPIOs. There are 4 GPIO "communities" on apollolake that each have a different ACPI device so return the appropriate name for the different communities. Change-Id: I596c178b7813ac6aaeb4f2685bb916f5b78e049b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14859 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13	soc/intel/apollolake: implement common gpio API	Aaron Durbin
	In order for apollolake mainboards to utilize the common GPIO API it actually needs to be implemented. Change-Id: I41de8d5d9f3c39e7e796eae73b01cb29e9c01347 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14797 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-04-14	soc/intel: Update license headers	Martin Roth
	Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-13	soc/intel/apollolake: add assert for pad constraints	Aaron Durbin
	Ensure the pads passed into the gpio functions are within range. Change-Id: Ic523cbfaf60a46709080347af3a36d6330f9a07c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13694 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13	soc/intel/apollolake: pre-evaluate gpio number values	Aaron Durbin
	To allow sharing macros in ASL as well as C the macros can't have complex expression because the ASL compiler does not evaluate those expressions. To that end, just pre-calculate the values. Lastly, add N_OFFSET and utilize it for symmetry. Change-Id: I546d71008e776b27ce8bcd24d2cbd2ee1b2d8020 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13693 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-11	soc/apollolake: Add minimal GPIO driver	Andrey Petrov
	This adds the minimal functionality needed to configure SoC pads. Change-Id: I2e2268eee2b8c822b42a48a95604b0fab86c9833 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13676 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)