coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-11-09	soc/intel/apollolake: Disable HECI1 before jumping to OS	Furquan Shaikh
	This change disables HECI1 device at the end of boot sequence. It uses the P2SB messaging to disable HECI1 device before hiding P2SB and dropping privilege level. BUG=b:119074978 BRANCH=None TEST=Verified that HECI1 device is not visible in lspci on octopus. Change-Id: Id6abfd0c71a466d0cf8f19ae9b91f1d3446e3d09 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08	Move compiler.h to commonlib	Nico Huber
	Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-20	pci: Move inline PCI functions to pci_ops.h	Patrick Rudolph
	Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-10	soc/intel/apollolake: Add file path check	Hannah Williams
	Fixes Coverity Issue: 1372243 Change-Id: Ib7e43b195357c723e1ae51f609a8b07ad984380a Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/20867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13	Rename __attribute__((packed)) --> __packed	Stefan Reinauer
	Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28	soc/pci_devs.h: Use consistent naming in soc/pci_devs.h	Subrata Banik
	This patch to make common PCI device name between APL and SKL. Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-15	soc/intel/apollolake: Cache FPF status value in flash	Andrey Petrov
	Since asking CSE to read FPF status turned out to be slow in some cases, cache and save returned value on first boot only. Value is read from flash on consequent boots. BUG=b:35586975 BRANCH=reef TEST=boot twice, make sure cached FPF status is loaded from flash the second time. Change-Id: I6e56a35407c9097616ccb05a557fded7b639c88a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18774 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09	soc/intel/apollolake: Add check if FPFs are blown	Andrey Petrov
	Apollolake platform comes with FPF (field-programmable-fuses). FPF can be blown only once, typically at the end of the manufacturing process. This patch adds code that sends a request to CSE to figure out if FPFs have already been blown. Change-Id: I9e768a8b95a3cb48adf66e1f17803c720908802d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18604 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09	soc/intel/apollolake: Prepare to use common HECI driver	Andrey Petrov
	Change-Id: Ib284493d886b223e8c85607de5fdb56b698fe5fa Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-08	soc/intel/apollolake: dump CSE status	Aaron Durbin
	Dump the CSE status registers for potential debugging purposes. Explicitly call out manufacturing mode of the part since it's important shipping devices ensure manufacturing mode is locked down. Intel is planning on writing a common driver so a complete status -> string dumps was not done because (surprise surprise) not all the fields are equal with previous implementations. BUG=chrome-os-partner:62177 BRANCH=reef TEST=Booted and noted dump of CSE status registers. Change-Id: I71d15722bb193877f1569c1d3e7f441302f5bd14 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18303 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>