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path: root/src/soc/intel/apollolake/bootblock
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2016-06-24soc/intel/apollolake: Implement global reset handlingAndrey Petrov
Global reset enable bit is not cleared on reset. Therefore, clear the bit early. Lock down 0xcf9 so that payload/OS can't issue global reset. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I3ddf6dd82429b725c818bcd96e163d2ca0acd308 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15199 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/apollolake: Move PMC BAR setup to bootblockAndrey Petrov
Some features of PMC needs to be accessed before romstage. Hence, move PMC BARs setup into bootblock. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I14493498314ef1a4ce383e192edccf65fed2d2cb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15332 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-22intel/apollolake: Add API for get_bios_size and use itFurquan Shaikh
get_bios_size returns the value of bios_size. Use this function to calculate bios_size for caching in bootblock. BUG=chrome-os-partner:54563 Change-Id: I2e592b1c52138bd4623ad2acd05c744224a8e50b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15292 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-21intel/apollolake: Enable SPI properly in bootblock and ramstageFurquan Shaikh
Bootblock: - Temporary BAR needs to be assigned for SPI device until PCI enumeration is done by ramstage which allocates a new BAR. - Call spi_init to allow bootblock/verstage to write/erase on flash. Ramstage: - spi_init needs to run in ramstage to allow write protect to be disabled for eventlog and NVRAM updates. This needs to be done pretty early so that any init calls(e.g. mainboard_ec_init) writing to flash work properly. Verified with this change that there are no more flash write/erase errors for ELOG/NVRAM. BUG=chrome-os-partner:54283 Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15209 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins)
2016-06-12bootblock: Declare common bootblock_pre_c_entry routineLee Leahy
Enable uses of a common bootblock_pre_c_entry routine. Pass in TSC value as a uint64_t value. TEST=Build for amenia and Galileo Gen2 Change-Id: I8be2e079ababb2cf1f9b7e6293f93e7c778761a1 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15124 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <lpleahyjr@gmail.com>
2016-06-03intel/apollolake: Clear TSEG reg early in bootblockFurquan Shaikh
TSEG register comes out of reset with a non-zero default value. This causes issues when cbmem_top returns non-zero value based on TSEG read before DRAM is initialized. Thus, clear TSEG reg early in bootblock to avoid unwanted side-effects. Change-Id: Id3c6c270774108e4caf56e2a07c5072edc65bb58 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15049 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-27soc/intel/apollolake: add support for verstageAaron Durbin
There previously was no support for building verstage on apollolake. Add that suport by linking in the appropriate modules as well as providing vboot_platform_is_resuming(). The link address for verstage is the same as FSP-M because they would never be in CAR along side each other. Additionally, program the ACPI I/O BAR and enable decoding so sleep state can be determined for early firmware verification. Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14972 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-19soc/apollolake: Pass earliest timestamp to timestamp_initAlexandru Gagniuc
We have a timestamp from before cache-as-ram setup saved in the MMX registers. Recover that timestamp, and use it as the base timestamp rather than letting lib/bootblock.c use a late timestamp. This allows more accurate profiling of the boot flow, since CAR setup time is no longer excluded from the timing information. Change-Id: I055092c600438c5260ab67509434a38f1eb77fe4 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14863 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-19soc/intel/apollolake: clear up ACPI timer emulation magic constantAaron Durbin
The timer emulation works by deriving a frequency based off the Common Timer Copy with a frequency of 19.2MHz. The desired frequency = (19.2MHz * multiplier) >> 32; With that knowledge update the code to let the compiler perform the necessary math based on target frequency. Change-Id: I716c7980f0456a7c6072bbaaddd6b7fcd8cd5b37 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14889 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18soc/intel/apollolake: Enable ACPI PM1 timer emulationAndrey Petrov
Enable emulation for ACPI PM1 timer. This is needed by FSP-M MemoryInit. Change-Id: I7a441f5f1673e6430697615ae7251da948e77548 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14821 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06Revert "soc/intel/apollolake: Enable LPC bus interface"Alexandru Gagniuc
This reverts commit e976bd44692d2adb320a1256f1b6bfaa6469108a. The LPC resource allocation will be completely reworked in subsequent patches. The most straightforward approach is to start by reverting the existing code. Change-Id: I2475542b79817020d4c956f22ed5856f05046b16 Reviewed-on: https://review.coreboot.org/14583 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-29soc/intel/apollolake: clarify Fast SPI CS2 pad configurationAaron Durbin
The pad for CS2 of the Fast SPI interface needs to be configured for automatic MMIO translation when a SPI TPM is utilized. Instead of unconditionally configuring that pad under LPC_TPM provide a explicit Kconfig for a mainboard to select. Change-Id: Ia94b90e12d71a4b849359188a853f7e036cc583b Signed-off-by: Aaron Durbin <adurbin@chormium.org> Reviewed-on: https://review.coreboot.org/14531 Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins)
2016-04-28soc/intel/apollolake: Add cache for BIOS ROMAndrey Petrov
Enable caching of BIOS region with variable MTRR. This is most useful if enabled early such as in bootblock. Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14480 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-28soc/intel/apollolake: Enable LPC bus interfaceAndrey Petrov
This adds early LPC setup in bootblock (for Chrome EC) as well as late (ramstage) IO decode/sirq enable. Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14469 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28soc/intel/apollolake: Configure a GPIO for TPM in bootblockAndrey Petrov
One of devices connected to FAST SPI bus is TPM. SoC uses dedicated line for chip select for TPM function. If TPM is used, that line needs to be configured to a specific native funciton. Change-Id: Ib5bf4c759adf9656f7b34540d4fc924945d27a97 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14467 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-21soc/intel/apollolake: Set default memory type to uncacheableFurquan Shaikh
Set the default memory type in MTRRCap register to 0. This ensures that even if the MTRR Enable bit is set in MTRRCap register, the default memory type is still uncacheable. Change-Id: I63e7993f8b65dabbab60e7c1bb8d6d89ef4da9ee Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14428 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-18soc/intel/apollolake: Do not re-save BIST resultFurquan Shaikh
BIST result is already stored by arch/x86/bootblock_ctr0.S in mm0. Also, eax does not contain BIST result by the time control reaches bootblock_pre_c_entry. bootblock_crt0.S saves timestamp in mm2 which was being overwritten here. Thus, remove the saving of BIST result from SoC code. Change-Id: I65444689cf104c59c84574019f5daf82aab10bc7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14381 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-14soc/intel: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-02soc/intel/apollolake: use CAR code coherency for all CAR stagesAaron Durbin
The flush L1D to L2 operation was only being used when loading romstage from bootblock. However, when the FSP-M component is loaded no code coherency actions are taken. I suspect this is because the FSP-M component is larger than the 24KiB L1D and the entry point is early in the image. Thus, when loading the FSP-M component the earlier part of the image is flushed out to L2 in the process of loading the latter part of the component. Also, once verstage is introduced the same code coherency actions need to be taken as well. Therefore, position the apollolake code to handle all these cases. Change-Id: Ie71764f1b420a6072c4f149ad3e37278b6cb70e1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14210 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-23soc/intel/apollolake: utilize postcar phase/stageAaron Durbin
The current Apollolake flow has its code executing out of cache-as-ram for the pre-DRAM stages. This is different from past platforms where they were just executing-in-place against the memory-mapped SPI flash boot media. The implication is that when cache-as-ram needs to be torn down one needs to be executing out of DRAM since the act of cache-as-ram going away means the code disappears out from under the processor. Therefore load and use the postcar infrastructure to bootstrap this process for tearing down cache-as-ram and subsequently loading ramstage. Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14141 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-02-26soc/intel/apollolake: implement bootblock_soc_early_init()Aaron Durbin
Provide a bootblock_soc_early_init() to that takes care of initializing the UART on behalf of the mainboard when serial console is enabled. Change-Id: I2d3875110b6f58a9e0b4c113084b85817aa05a87 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13793 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-16soc/intel/apollolake: bootblock: implement platform_prog_run()Andrey Petrov
Once bootblock copied romstage into CAR it may not jump into it right away. This is because we are in NEM mode, there is no backing store and a miss in L1 may cause L1D line snoop that gets written back. The solution is to flush L1D to L2 so snoop guaranteed to hit L2. Change-Id: I2ffe46dbfdfe7f0ccd38b34ff203ff76b6d5755b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13703 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLEAndrey Petrov
Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11soc/apollolake: Add initial cache-as-ram setup for bootblockAlexandru Gagniuc
This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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