coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2016-06-20	soc/apollolake: Include PCI _OSC method	Hannah Williams
	Change-Id: I2545fc184ebfaa006a75783bf3d55f009066eed3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15110 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-01	intel/apollolake: Add support to enable google ChromeEC	Shaunak Saha
	ChromeEC is needed for EC controlled features to work properly. This patch adds neccessary support in soc/intel so that mainboard asl files can include the ChromeEC e.g. PNOT method and LPCB and also the nvs fields. BUG = 53096 TEST = This patch is needed by the mainboard specific ASL change to include src/ec/google/chromeec/acpi/ec.asl Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/14967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25	soc/apollolake: Enable Wake from USB devices	Hannah Williams
	Change-Id: Ib0b30a5779681488e80000a2570fc2fd4c69e908 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14893 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28	soc/intel/apollolake: Add GPIO devices	Zhao, Lijian
	Add GPIO controller in ACPI device description. GPIO controller driver is probed in kernel and all the pins in the banks are showing respective values. Change-Id: I0512cfec872113b15fd204ec3b95efeac87f694a Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/14478 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28	soc/intel/apollolake: Actually include ACPI PCI IRQ definitions	Andrey Petrov
	Without ACPI PCI IRQ definitions kernel is left only with informaiton available in PCI config space, which is not sufficient. Change-Id: I3854781049851b5aa5b2dbf3257ece2fee76c3e2 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-16	intel/apollolake: Fix whitespace issues	Martin Roth
	Change-Id: Ia5bcd19d994e23375d7e6d2050113c809ae57296 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14368 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-14	soc/intel: Update license headers	Martin Roth
	Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-11	soc/intel/apollolake: Add lpss dsdt entry	Zhao, Lijian
	Add southbridge and LPSS device DSDT table. Change-Id: I0607398408900d8c5d543ecd5e5d4830d2a70bf1 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/14218 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>