coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-07-21	soc/intel/apollolake: Bring in delta for GLK SOC	Hannah Williams
	Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-03	soc/intel/apollolake: Use common gpio for apollolake	Hannah Williams
	No regression observed on a APL platform Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13	soc/intel/apollolake: Change IOSF_BASE_ADDRESS to PCR_BASE_ADDRESS	Furquan Shaikh
	With recent change to use common block PCR (ccd8700c), IOSF_BASE_ADDRESS was renamed to PCR_BASE_ADDRESS. However, SD card change (99ce8a9b) was not rebased on top of it, so IOSF_BASE_ADDRESS slipped into the tree. Fix this by replacing all occurrences of IOSF_BASE_ADDRESS by PCR_BASE_ADDRESS. Change-Id: I40eb07be306035c940fc960896e0807d6c73bafa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19277 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-13	soc/intel/apollolake: Set sdcard card detect (CD) host ownership	Venkateswarlu Vinjamuri
	Currently sdcard CD host ownership is always owned by the GPIO driver. Due to this sdcard detection fails during initial boot process and OS fails to boot from sdcard. This implements change in host ownership from acpi to GPIO driver when kernel starts booting. BUG=b:35648535 TEST=Check OS boot from sdcard. Change-Id: I042a8762dc1f9cb73e6a24c1e7169c9746b2ee14 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18947 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2016-09-14	soc/intel/apollolake: Add PM methods to power gate PCIe	Vaibhav Shankar
	This implements GNVS variable to store the address of PERST_0, _ON/_OFF methods to power gate PCIe during S0ix entry, and PERST_0 assertion/de-assertion methods. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>