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path: root/src/soc/intel/alderlake
AgeCommit message (Expand)Author
2021-09-16soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_TCSS at SoC levelSubrata Banik
2021-09-16soc/intel/alderlake: Add igd deviceWisley Chen
2021-09-10soc/intel/alderlake: Align board type as per FSP v2347_00Ronak Kanabar
2021-09-10soc/intel/alderlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
2021-09-10soc/intel/alderlake: Set LpmStateEnableMask UPDTim Wawrzynczak
2021-09-10soc/intel/alderlake: Add get_adl_cpu_type functionTim Wawrzynczak
2021-09-09soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiBMAULIK V VAGHELA
2021-09-09soc/intel/alderlake: Enable Irms UPD for ADLRonak Kanabar
2021-09-08cpu/x86/tsc: Deduplicate Makefile logicAngel Pons
2021-09-06soc/intel/adl: Move USB4 hotplug Kconfig to commonFurquan Shaikh
2021-09-05soc/intel/alderlake: Add tpch device information under dptfSumeet Pawnikar
2021-09-03soc/intel/alderlake: set power limits dynamically for thermalSumeet Pawnikar
2021-09-01soc/intel/alderlake: Fix processor hang while plug unplug of TBT deviceSugnan Prabhu S
2021-08-26soc/intel/alderlake: Lock PAM registers in finalizeTim Wawrzynczak
2021-08-20soc/intel/adl: Update power limits for ADL-M SKUSumeet Pawnikar
2021-08-20soc/intel/adl: Update PCI ID for ADL-M SKUSumeet Pawnikar
2021-08-19soc/intel/alderlake: Move INTEL_CAR_NEM selection from SoC to mainboardSubrata Banik
2021-08-19soc/intel/alderlake: set default PL4 values for different SKUsSumeet Pawnikar
2021-08-16soc/intel/alderlake: Create eNEM Kconfig for Alder LakeSubrata Banik
2021-08-12soc/intel/alderlake: Clean up FSP chipset lockdown configurationFelix Singer
2021-08-12soc/intel/alderlake: Configure the SKU specific parameters for VR domainsV Sowmya
2021-08-12soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADLV Sowmya
2021-08-11soc/intel/alderlake: Implement report_cache_info() functionSubrata Banik
2021-08-10mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cbMAULIK V VAGHELA
2021-08-05soc/intel/alderlake: Add GFx Device ID 0x46aaBora Guvendik
2021-08-04Move post_codes.h to commonlib/console/Ricardo Quesada
2021-08-03soc/intel/*: Allow configuring 8254 timer via CMOSSean Rhodes
2021-07-28util/spd_tools/lp4x: Add new memory parts and generate SPDsDavid Wu
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
2021-07-20soc/intel/alderlake: Add support for I2C6 and I2C7Varshit B Pandya
2021-07-19soc/intel/common: Rename kconfig PMC_EPOCLean Sheng Tan
2021-07-17soc/intel/alderlake: Select INTEL_GMA_OPREGION_2_1Meera Ravindranath
2021-07-17soc/intel/alderlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik
2021-07-15soc/intel/alderlake: Add virtual GPIOs for community 1Maulik V Vaghela
2021-07-15soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDsSubrata Banik
2021-07-14soc/intel/alderlake: Add GFx Device ID 0x46a6Maulik V Vaghela
2021-07-13soc/intel/alderlake: Implement WA for DDR5 DIMM modulesMeera Ravindranath
2021-07-13soc/intel/alderlake: Add (and fix) devices in IRQ tableTim Wawrzynczak
2021-07-12soc/intel/alderlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KBSubrata Banik
2021-07-12soc/intel/alderlake: Add missing devices to pci_devs.hTim Wawrzynczak
2021-07-12soc/intel/alderlake: Set max Pkg C-states to AutoV Sowmya
2021-07-08soc/intel/alderlake: Avoid NULL pointer deferenceJohn Zhao
2021-07-05soc/intel/alderlake: Add support to update the FIVR configsV Sowmya
2021-07-05soc/intel/alderlake: Correct Bus and Device of Touch Host ControllerVarshit B Pandya
2021-07-02src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons
2021-07-02soc/intel/alderlake: Add USB TCSS enablementBernardo Perez Priego
2021-07-01soc/intel/alderlake: Enable energy efficiency turbo modeV Sowmya
2021-07-01soc/intel: Refactor `xdci_can_enable()` functionAngel Pons
2021-07-01soc/intel/alderlake: Select VBOOT_X86_SHA256_ACCELERATION configSubrata Banik
2021-06-30soc/intel/alderlake: Send End-of-Post message to CSETim Wawrzynczak
2021-06-30soc/intel/common: Move PMC EPOC related code to Intel common codeLean Sheng Tan
2021-06-30src: Move `select ARCH_X86` to platformsAngel Pons
2021-06-29soc/intel/alderlake: Enable support for common IRQ blockTim Wawrzynczak
2021-06-28soc/intel: Drop casts around `soc_read_pmc_base()`Angel Pons
2021-06-25soc/intel/alderlake: Fix the typo for FSP_S_CONFIG paramV Sowmya
2021-06-25soc/intel/alderlake: Update s0ix cstate tableBernardo Perez Priego
2021-06-24soc/intel/alderlake: Update mainboard_memory_init_params() argumentSubrata Banik
2021-06-24soc/intel/alderlake: Refactor soc_silicon_init_params functionSubrata Banik
2021-06-24soc/intel/alderlake: Rename FSP_S_CONFIG variable from params to s_cfgSubrata Banik
2021-06-24soc/intel/alderlake: Refactor platform_fsp_silicon_init_params_cb functionSubrata Banik
2021-06-23soc/intel/alderlake: Use devfn_disable() function for XDCISubrata Banik
2021-06-21soc/intel/alderlake: Add GFx Device ID 0x46b3Meera Ravindranath
2021-06-18soc/intel/alderlake: Add TBT PCIe root ports enablementBernardo Perez Priego
2021-06-17soc/intel/{alderlake,tigerlake}: Fix typo in pmc.hWerner Zeh
2021-06-17soc/intel/alderlake/romstage: Refactor soc_memory_init_params functionSubrata Banik
2021-06-16soc/intel/alderlake/romstage: Update display UPDs based on InternalGfxSubrata Banik
2021-06-16soc/intel/alderlake: Make use of is_devfn_enabled() functionSubrata Banik
2021-06-11soc/intel/{common,alderlake}: Use generic name "Alderlake Platform"Sridhar Siricilla
2021-06-08soc/intel/alderlake/romstage: Drop ineffective FSP-M UPD `ChHashMask`Subrata Banik
2021-06-08soc/intel/alderlake: Set SaIpuEnable UPD according to devicetreeTim Wawrzynczak
2021-06-08soc/intel: Add Alder Lake's GT device IDSridhar Siricilla
2021-06-08soc/intel/alderlake: Correct TCSS XHCI Port status offsetSridhar Siricilla
2021-06-07cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki
2021-06-07soc/intel/adl: Add SKU specific power limits supportSumeet Pawnikar
2021-06-07soc/intel/alderlake: Update ACPI device ID of IOMMaulik V Vaghela
2021-06-07soc/intel: Drop unused lpss functionsFurquan Shaikh
2021-06-07soc/intel/alderlake: Set Base Addresses for TBT DMA remapping enginesSridhar Siricilla
2021-06-05soc/intel/alderlake: Add IDE-R and KT device into chipset.cbSubrata Banik
2021-06-04soc/intel/alderlake: Add PMC ACPI interfaceTim Wawrzynczak
2021-06-03soc/intel/alderlake: Add new memory parts for ADL boardsAmanda Huang
2021-05-30soc/intel/alderlake: Add placeholder SPD fileTim Wawrzynczak
2021-05-26soc/intel/alderlake: Update soundwire master countSugnan Prabhu S
2021-05-26soc/intel/alderlake: Add validity for TBT firmware authenticationJohn Zhao
2021-05-25soc/intel/alderlake: Fix SA_DEVFN_CPU_PCIE6_*Tim Wawrzynczak
2021-05-21soc/intel/common: Add Alder Lake device IDsSumeet R Pawnikar
2021-05-18soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.aslMaulik V Vaghela
2021-05-18cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans
2021-05-18soc/intel/alderlake: mb/intel/sm: Add tcss codeDeepti Deshatty
2021-05-16soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwardsBora Guvendik
2021-05-16vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00Ronak Kanabar
2021-05-14soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela
2021-05-14soc/intel/alderlake: Add known GPIO virtual wire informationDeepti Deshatty
2021-05-14soc/intel/alderlake: Add known CPU Port IDs for GPIO communitiesDeepti Deshatty
2021-05-14soc/intel/alderlake: Add IOM PCR PIDDeepti Deshatty
2021-05-13src: Match array format in function declarations and definitionsPatrick Georgi
2021-05-10soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetrainingMaulik V Vaghela
2021-05-07soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXITKane Chen
2021-05-07soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmasterKane Chen
2021-05-06soc/intel/alderlake: Add CrashLog implementation for Intel ADLFrancois Toguo
2021-05-05soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIOMaulik V Vaghela