| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-01-25 | soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config | Subrata Banik |
| 2021-05-07 | soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster | Kane Chen |
| 2020-10-03 | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |