coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-02-05	soc/intel/alderlake: Refactor PCIE port config	Eric Lai
2021-01-21	soc/intel/alderlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGD	Subrata Banik
2021-01-10	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	Subrata Banik
2020-12-04	src/soc/intel/alderlake: Enable the PCH HDA	V Sowmya
2020-10-25	soc/intel/alderlake/romstage: Skip GPIO configuration from FSP	Subrata Banik
2020-10-14	soc/intel/alderlake: Enable TME for Alder Lake	Subrata Banik
2020-10-05	soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()	Nick Vaccaro
2020-10-05	mb, soc: change mainboard_get_dram_part_num() prototype	Nick Vaccaro
2020-10-03	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	Subrata Banik
2020-09-24	soc/intel/alderlake/romstage: Fix compilation issue	Subrata Banik
2020-09-15	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	Subrata Banik