coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-02-05	soc/intel/alderlake: Refactor PCIE port config	Eric Lai
	Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-21	soc/intel/alderlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGD	Subrata Banik
	Make IGD disable when mainboard user selects SOC_INTEL_DISABLE_IGD. TEST=Able to get depthcharge pre-OS splash screen with AMD Radeon RX 5700 PCI-E DGPU when mainboard user selects SOC_INTEL_DISABLE_IGD. Change-Id: Ibbe9c8c4d77018de83815d7d203284b1fbc0da58 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-10	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	Subrata Banik
	List of changes: 1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per EDS. 2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards. 3. Rename PcieRpEnable to PchPcieRpEnable. 4. Enable CPU RPs as below in mainboard devicetree.cb RP1: PEG60 : 0:6:0 : CPU SSD1 RP2: PEG10 : 0:1:0 : x8 CPU Slot RP3: PEG62 : 0:6:2 : CPU SSD2 Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04	src/soc/intel/alderlake: Enable the PCH HDA	V Sowmya
	This patch enables the PCH HDA device based on the devicetree configuration. Change-Id: I1791b769f4ab41cf89d82cf59049a2980c6c1eb0 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48272 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25	soc/intel/alderlake/romstage: Skip GPIO configuration from FSP	Subrata Banik
	Set GpioOverride UPD to 1 to skip GPIO configuration in FSP phases TEST=Able to build and boot ADLRVP to OS. Change-Id: Ie965a85d9da9b6a23b385536313b852e66909cf4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-14	soc/intel/alderlake: Enable TME for Alder Lake	Subrata Banik
	List of changes: 1. Select CONFIG_INTEL_TME from SoC Kconfig 2. Set TmeEnable FSP-M UPD based on Kconfig. TEST=Able to build and boot ADLRVP and verified from Chrome OS that TME is enable. Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46296 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	Subrata Banik
	List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-24	soc/intel/alderlake/romstage: Fix compilation issue	Subrata Banik
	Refer to commit 490546f (soc/intel: rename get_prmrr_size) for details. Change-Id: I4a83feedcdb337ba9613a07215196bc223fb46d1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45651 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	Subrata Banik
	List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Add SA EDS document number and chapter number 4. Fill required FSP-M UPD to call FSP-M API Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>