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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I852d6daebdcb8461c18e7c0eaf1c54ad7c59c0c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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These were hidden because no Windows drivers existed, but now that
they do, the ACPI devices need to be visible in order for the
drivers to properly attach.
TEST=build google/banshee, boot Windows, verify Windows drivers
correctly attach to PCM/IOM devices.
Change-Id: Idbbaee29bffb49059d8450abd09e0c3f7b490fae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74850
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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This patch replaces static index 0 for PMC read resources with PCI
configuration offset 0x10 (PWRMBASE).
TEST=Able to build and boot Google, Rex to OS.
Without this change:
[SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 0
With this change:
[SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iee2523876a8045e70effd5824afc327d1113038b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Hide these ACPI device so Windows does not warn about missing device
drivers.
Change-Id: Iba6cf7a17eefc9f4f247621f6625151f2fd5f3a7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.
Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch implements the required operations to perform prior to
booting to OS using coreboot native driver when platform decides
to skip FSP notify APIs, i.e., Ready to Boot and End Of Firmware.
Additionally, move the PMCON status bit clear operation to `.final` ops
to cover any such chances where FSP-S Notify Phase or any other later
boot stage may request a global reset and PMCON status bit remains set.
BUG=b:211954778
TEST=Able to build brya with these changes.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Since it's just a one-liner, implement disabling of the ACPI timer in
soc code. This reduces complexity.
Change-Id: I434ea87d00f6e919983d9229f79d4adb352fbf27
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Move disabling of PM Timer to SoC PMC code.
The original reason for placing that in `finalize` [1] was FSP hanging
due to use of the PM timer without enabling timer emulation first in
coreboot, which was added later [2].
[1] commit 6c1bf27dae (intel/skylake: disable ACPI PM Timer to enable
XTAL OSC shutdown)
[2] commit f004f66ca7 (soc/intel/skylake: Enable ACPI PM timer emulation
on all CPUs)
Change-Id: I354c3aea0c8c1f8ff3d698e0636932b7b76125f7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The current names of the PMC init/enable callbacks are very confusing.
Rename them.
Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The pep.asl file is being obsoleted by runtime generation, therefore
switch alderlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Move PMC EPOC related code to intel/common/block because it is
generic for most Intel platforms and ADL, TGL & EHL use it.
Add a kconfig 'PMC_EPOC' to guard this common EPOC code.
The PMC EPOC register indicates which external crystal oscillator is
connected to the PCH. This frequency is important for determining the
IP clock of internal PCH devices.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ib5fd3c4a648964678ee40ed0f60ca10fe7953f56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This ACPI interface is required by e.g., the intel/common/pcie/rtd3
driver, which is used by some alderlake boards.
BUG=b:190080798
TEST=disassemble SSDT and find \_SB.PCI0.PMC.IPCS
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I59eae47e623587d35e394c9bff21481fcad2d6b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55172
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On tgl, we noticed system hang if a shutdown is triggered before fsps.
The dut is unable to shutdown properly due to tcss is stuck before
tcss_init in fsps.
This change enable power button smi on jsl, tgl, adl after fsps.
it can also prevent a shutdown failure due to lack of fsps init on
certain ip.
BUG=b:186194102, b:186815114
TEST=Power on the system and pressing power button repeatedly doesn't
cause the system hang during shutdown.
Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API
Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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