index
:
coreboot.git
macbookair5_2
macbookpro10_1
master
mbp101_medisable
mbp101_medisable_1
mbp82
my copy of coreboot
gitea
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
soc
/
intel
/
alderlake
/
p2sb.c
Age
Commit message (
Expand
)
Author
2020-09-15
soc/intel/alderlake/romstage: Do initial SoC commit till romstage
Subrata Banik
