| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-11-29 | soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration | Sridhar Siricilla |
| 2020-10-29 | mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg' | Subrata Banik |
| 2020-09-15 | soc/intel/alderlake/romstage: Do initial SoC commit till romstage | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |