coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2022-05-05	soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done	Subrata Banik
	This patch calls into the PMC IPC function that informs about PMC enumeration. Note: Alder Lake FSP Notify Phase 1 callback missed to send this PMC IPC, hence, this patch is considered as an improvement over FSP Notify Phase API. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS without any PMC IPC error. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I43cfad25a5861c5aa5dae293ff42c9cefe862ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-04-27	soc/intel/alderlake: Implement PCH lock down configuration	Subrata Banik
	This patch implements a function to enable IOSF Primary Trunk Clock Gating. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-27	soc/intel/alderlake: Implement PMC feature lock	Subrata Banik
	This patch locks PMC features like: debug mode configuration and host read access to PMC XRAM. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-27	soc/intel/alderlake: Implement PMC soft strap interface lock	Subrata Banik
	This patch performs locking of the PMC soft strap message interface. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified Bit 0 of PMC MMIO register 0x104c is set as below. > localhost ~ # iotools mmio_read32 0xfe00104c 0x00000001 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1ae972a203affa54c03de71f0f702356334cbf7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-27	soc/intel/alderlake: Implement PMC static function lock	Subrata Banik
	This patch performs PMC static function lockdown. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified PMC static PG lock (bit 31) is set. > iotools mmio_read32 0xfe001e20 0x80000000 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I68343f9af4f34aceae06293c5f87c5eaa3430a60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-23	soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function	Subrata Banik
	This patch refactors the `pmc_lockdown_cfg()` to remove the helper functions and uses the `setbits32` function to enforce bit locking as applicable. BUG=b:211954778 TEST=Able to build google/redrix with these changes and boot to OS. > localhost ~ # iotools mmio_read32 0xfe0018c4 0x85000000 (bit 31 is set) > localhost ~ # iotools mmio_read32 0xfe001024 0x00062610 (bits 4, 17 and 18 are set) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	Subrata Banik
	List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>