coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-11-29	soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration	Sridhar Siricilla
2020-10-29	mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'	Subrata Banik
2020-10-24	{cpu,soc}/intel: deduplicate cpu code	Michael Niewöhner
2020-10-21	soc/intel: convert XTAL frequency constant to Kconfig	Michael Niewöhner
2020-10-06	soc/intel/alderlake/ramstage: Fix compilation issue	Subrata Banik
2020-10-05	soc: move mainboard_get_dram_part_num prototype to memory_info.h	Nick Vaccaro
2020-10-05	mb, soc: change mainboard_get_dram_part_num() prototype	Nick Vaccaro
2020-10-03	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	Subrata Banik
2020-09-27	soc/intel/alderlake: Add GPIOs for Alder Lake SOC	Subrata Banik
2020-09-15	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	Subrata Banik
2020-09-10	soc/intel/alderlake: Rename pch_init() code	Subrata Banik
2020-09-05	soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock	Subrata Banik