coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-03-27	soc/intel/alderlake: Correct GPE DWx assignment as per EDS	Subrata Banik
	List of changes: 1. Update GPIO Group to GPE DWx assignment encoding as per MISCCFG register per GPIO Community. 2. PMC_GPP_* macros are also updated as per GPIO_CFG register in PMC space. BUG=b:183464235 TEST=Able to fix the TPM IRQ issue on SM. Change-Id: Id9f57b0b5726315f5ebba013f11d52ed3ee34484 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51789 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27	soc/intel/alderlake: Add GPIOs for Alder Lake SOC	Subrata Banik
	Add definitions for the GPIO pins on Alder Lake LP, as well as GPIO IRQ routing information and supporting ACPI ASL. For now, add the following 5 GPIO communities and 13 GPIO groups: Comm. 0: GPP_B, GPP_T, GPP_A Comm. 1: GPP_S, GPP_H, GPP_D Comm. 2: GPD Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS Comm. 5: GPP_R, GPP_SPI0 Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>