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Add definitions for the GPIO pins on Alder Lake LP,
as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following 5 GPIO communities and 13 GPIO groups:
Comm. 0: GPP_B, GPP_T, GPP_A
Comm. 1: GPP_S, GPP_H, GPP_D
Comm. 2: GPD
Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS
Comm. 5: GPP_R, GPP_SPI0
Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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