| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-05-14 | soc/intel/alderlake: Add known GPIO virtual wire information | Deepti Deshatty |
| 2021-05-14 | soc/intel/alderlake: Add known CPU Port IDs for GPIO communities | Deepti Deshatty |
| 2021-05-05 | soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO | Maulik V Vaghela |
| 2021-03-27 | soc/intel/alderlake: Correct GPE DWx assignment as per EDS | Subrata Banik |
| 2020-09-27 | soc/intel/alderlake: Add GPIOs for Alder Lake SOC | Subrata Banik |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |