coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-03-30	soc/intel/alderlake: Avoid reprogramming the SRAM BAR	Subrata Banik
	This patch avoids the redundant programming of SRAM BAR when the SRAM PCI device is enabled. Rather read the PCH SRAM Base Address Register while enabling crashlog feature. Additionally, this patch relies on PCI enumeration to get the SRAM BAR rather than hijacking the SPI temporary base address which might have resulted in problems if SPI is disabled on some platform with BAR being implemented. TEST=Able to build and boot google/marasov and crashlog is working. Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-20	soc/intel/*/crashlog.[ch]: Remove unused includes	Elyes Haouas
	Change-Id: I126d49c27302e1ed2e00ff491d59cadda7101d12 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70924 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-22	soc/intel: Remove unused <cbmem.h>	Elyes HAOUAS
	Change-Id: I529c822c9e952dae6613d3de64f6709e0fd9b385 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05	src/soc/intel: Remove unused <delay.h>	Elyes HAOUAS
	Change-Id: Id8e6221a9801d5198171dc9cd564000d19720a42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-23	soc/intel/alderlake: remove tmp bar assignment for cpu crashlog	Kane Chen
	When the cpu_cl_discovery is called, coreboot actually assigns a BAR to cpu crashlog pci device. Hence, we don't need to assign a tmp BAR for cpu crashlog pci device BUG=b:195327879 TEST=Found BERT table is created and the tcss function is ok in depthcharge Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08	soc/intel/alderlake: Avoid NULL pointer deference	John Zhao
	Coverity detects dereference pointers req and res that are NULL when calling the pmc_send_ipc_cmd function. This change prevents NULL pointers dereference. Found-by: Coverity CID 1458077, 1458078 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-06	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	Francois Toguo
	This enables CrashLog for Intel ADL based platform. BUG=b:183981959 TEST=CrashLog data generated, extracted, processed and decoded sucessfully on adl-m RVP. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I15ba0b41f73c1772f09584f13bcf5585caa90782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52454 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>