coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-10-01	soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU	Sumeet Pawnikar
2021-09-29	soc/intel/alderlake: Add ADLP 242 power configurations	Tracy Wu
2021-09-03	soc/intel/alderlake: set power limits dynamically for thermal	Sumeet Pawnikar
2021-08-20	soc/intel/adl: Update power limits for ADL-M SKU	Sumeet Pawnikar
2021-08-19	soc/intel/alderlake: set default PL4 values for different SKUs	Sumeet Pawnikar
2021-08-10	mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cb	MAULIK V VAGHELA
2021-07-20	soc/intel/alderlake: Add support for I2C6 and I2C7	Varshit B Pandya
2021-07-05	soc/intel/alderlake: Correct Bus and Device of Touch Host Controller	Varshit B Pandya
2021-06-07	soc/intel/adl: Add SKU specific power limits support	Sumeet Pawnikar
2021-06-05	soc/intel/alderlake: Add IDE-R and KT device into chipset.cb	Subrata Banik
2021-05-06	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	Francois Toguo
2021-03-15	soc/intel/alderlake: Remove obsolete CNVi Bluetooth PCI device	Cliff Huang
2021-03-05	soc/intel/adl, mb/google/brya: Add IPU to devicetree	Tim Wawrzynczak
2020-12-30	soc/intel: hook up new gpio device in the soc chips	Michael Niewöhner
2020-12-29	soc/intel/alderlake: Update chipset.cb for TCSS and USB	Eric Lai
2020-12-04	soc/intel/alderlake: Align chipset.cb with pci_devs.h	Eric Lai
2020-11-30	soc/intel/alderlake: Add initial chipset.cb	Tim Wawrzynczak