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According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds the required gpio operations struct to soc/common gpio
code and hooks them up in all socs currently using the gpio block code,
except DNV-NS, which is handled in a separate change.
Also, add the gpio device to existing chipset devicetrees.
Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with
CB:48711 and OCP DeltaLake with CB:48672.
Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API
Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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