summaryrefslogtreecommitdiff
path: root/src/soc/intel/alderlake/acpi
AgeCommit message (Collapse)Author
2024-09-04soc/intel: Refactor ITSS macrosSubrata Banik
This patch refactors ITSS related SoC specific macros by consolidating them into a common itss.h file. This improves code maintainability and reduces redundancy as each SoC previously defined the same macros. Specific changes include: - Move SoC specific ITSS macros into intelblocks/itss.h. - SoC code now includes intelblocks/itss.h instead of the SoC-local soc/itss.h. - Drop soc/itss.h from static ASL files. - Delete soc/itss.h from all SoC locals except Apollo Lake and Sky Lake. TEST=Able to build and boot google/hatch, google/xol and google/karis. Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-02-22soc/intel/alderlake: Remove Alder Lake M SKUSean Rhodes
ADL-M is not commercially available, so it can be removed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If769989f7a0434e32ebbcc8eac9b965b70ca71ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/80614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-18soc/intel/alderlake/acpi: Drop ACPI stub for SATA deviceMatt DeVillier
This is now generated by acpigen in the common/block/sata module. Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-02soc/intel/*: Correct ACPI device name for eMMCMatt DeVillier
The ACPI name of any device needs to match the name used for generating the S0i3 LPI constraint list, which comes from soc_acpi_name() for each SoC. The names used for the eMMC controller do not match, which will lead to broken ACPI tables since the LPI constriant will reference an ACPI device which does not exist. Some OSes tolerate this better than others, but it should still be corrected. TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify no invalid device names referenced. Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78825 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-04soc/intel: Move USB wake methods to a common ASL fileReka Norman
The ACPI methods for enabling USB wake are identical on ADL, CNL and SKL. Move them to a common ASL file so they can be reused more easily on other SoCs. Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks in devicetree to a common header. BUG=b:300844110 TEST=Use abuild to build kinox, puff, and fizz with and without this change. Check the generated dsdt.aml is unchanged. Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-13soc/intel/{tigerlake,alderlake,meteorlake}: Start to unify the TCSS ACPISean Rhodes
The ACPI used for Tiger Lake, Alder Lake and Meteor Lake are very similar, so can be moved to shared code. This commit aligns minor difference between then, such as comments and tabs/spaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If6554c7ef9e83740d7ec5dcca6a9d7e32fb182db Reviewed-on: https://review.coreboot.org/c/coreboot/+/77453 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13soc/intel: Rename pcr.asl to pch_pcr.aslSubrata Banik
The PCR (Private Configuration Register) is applicable to access the P2SB register space starting with the Intel SkyLake generation of SoC. Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in SoC die (same as PCH die for U/H SoC) and another in IOE die. This patch renames pcr.asl to pch_pcr.asl to reflect the actual source of the P2SB IP in the die (i.e., SoC die or PCH die). BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-01soc/intel/adl: Unhide PMC, IOM ACPI devices from OSMatt DeVillier
These were hidden because no Windows drivers existed, but now that they do, the ACPI devices need to be visible in order for the drivers to properly attach. TEST=build google/banshee, boot Windows, verify Windows drivers correctly attach to PCM/IOM devices. Change-Id: Idbbaee29bffb49059d8450abd09e0c3f7b490fae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74850 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-19soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Rename it to D3COLD_SUPPORT to make it clear what it's doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-12Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol"Michael Niewöhner
This reverts commit fd4ad29f1824ad5d8df67f3e30d3908d24cbd8a4. Reason for revert: dependency for revert CB:73903 Change-Id: I5ed5e3e267032d62d65aef7fb246a075dccc9cf6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-26soc/intel: Move USB PORTSC definition into IA common codeSubrata Banik
This patch moves USB Port Status and Control (PORTSC) Reg definition into IA common code to allow other SoC code to reuse it without redefining the same for each SoC. TEST=Able to build and boot google/taeko where USB wake is working. Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-04soc/intel/alderlake: Add UWES ASL into xhci.aslScott Chao
Align support for enable wake-on-usb attach/detach as was introduced in Cannon Lake in commit 811284125f0a ("soc/intel/cannonlake: Add UWES ASL into xhci.asl"). This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree. BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <Scott_Chao@wistron.com> Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-01soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbolSean Rhodes
Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with the D3COLD_SUPPORT symbol, as it allows for more granular control. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-14soc/intel/alderlake: Add missing SATA DSDT devicePatrick Rudolph
Add "SATA" to DSDT as it's referenced by Intel PEP SSDT. Fixes warning shown in Linux: ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_SB_.PCI0.SATA (20220331/dspkginit-438) Change-Id: I65a1d17bce246022859f011cdc4712e1206a98fe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72762 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-09Revert "device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT"Felix Singer
This reverts commit d6e04aa00bc5a8912a041a569eb57f6962d1119a. Reason for revert: Breaks master. Change-Id: If7daeaaffe3f9ae9f5e2fbecef5817b9b62827d3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72917 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-08device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORTSean Rhodes
Add NO_S0IX_SUPPORT for boards that do not support, or do not want to support S0IX. As all the boards in the tree that do this, don't support D3Cold, add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is selected to disable D3Cold support. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04abc7efe2db06ae6daba9e09835441b62ee44f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-08soc/intel/{tgl,adl}/acpi: Unify the way D3Cold is enabledSean Rhodes
Both Alder Lake and Tiger Lake have Kconfig options for S3, which disables support for D3Cold. Unify these so that they are easier to compare. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6eaba99e5483053a91ca20df2b7788edac5d65b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72798 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07soc/intel/alderlake: Remove unused S0IX variableSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I85fc5dabf10c6df7f11fd1defe8a39afc9f95325 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72797 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCMSean Rhodes
Software Connection Manager doesn't work with Linux 5.13 or later, resulting in TBT ports timing out. Not advertising this results in Firmware Connection Manager being used and TBT works correctly. Add Kconfig options to chose between SCM (Software Connection Manager) and FCM (Firmware Connection Manager). FCM is primary, as it's more compatible save for ChromeOS devices as ChromeOS uses SCM. Linux patch: torvalds/linux@c6da62a c6da62a219d028de10f2e22e93a34c7ee2b88d03 Tested with StarBook Mk VI (i7-1260P). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-27soc/intel/alderlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include intelblocks/gpio.h BUG=b:261778357 TEST=Able to build and boot Google/brya. Change-Id: Ia90a8ea7b4ee125657c7277e3e14018cfe5423a9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71266 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21soc/intel/{adl,mtl,tgl}: Drop unnecessary `dptf.asl`Subrata Banik
This patch drops unused `dptf.asl` from the latest IA SoC platforms as DPTF ACPI code generation is now relies on runtime aka SSDT rather than having fixed dptf.asl files to include inside the mainboard dsdt.asl. TEST=Able to build Google/Kano without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I30a53eace89bf5324d7c2f15c6c2d2218f90eaf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71087 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-12soc/intel/adl/acpi: add entries for HEC1 and SRAM to DSDTAnil Kumar
HEC1 and SRAM are defined in src/soc/intel/alderlake/chipset.cb: device pci 16.0 alias heci1 on end device pci 14.2 alias shared_sram off end This patch adds entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors from kernel TEST=Built and tested on brya to confirm errors are not seen. BUG=b:260258765 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ifd9c509e82ccf02a7801d51513597fe2e5d9e631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70454 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel: Move TCSS FW latency macros to IA common tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from SoC specific tcss.h to IA common tcss.h Additionally, ensure other structure definitions belonging to the IA common code tcss.h are not causing compilation issues for ASL files (due to including FW latency macros) hence, guarded against `!defined(__ACPI__)`. TEST=Able to build and boot Google/Rex and Google/Kano. Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/alderlake: Move TCSS FW latency macros to tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from `tcss_pcierp.asl` to SoC specific `tcss.h`. TEST=Able to build and boot Google/Kano. Change-Id: I96db2dbf050c8f09e4d9c4018a2caa286f7ef1d1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70485 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25soc/intel/adl/acpi: add FSPI to DSDTEran Mitrani
A previous CL ("Add missing ACPI device path names", commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors from the Kernel on Brya devices (see Tim's comment on patchset 8): > ACPI Error: AE_NOT_FOUND, While resolving a named reference > package element - \_SB_.PCI0.FSPI FSPI is defined in src/soc/intel/alderlake/chipset.cb: device pci 1f.5 alias fast_spi on end This CL adds the corresponding FSPI device to the DSDT to prevent the error mentioned above. TEST=Built and tested on brya by verifying the error is gone. BUG=b:231582182 Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69920 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20soc/intel/alderlake: Drop local `ufs.asl`Subrata Banik
This patch drops `ufs.asl` from the local SoC directory. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I84e0b51e74e2d6a7120f1d990152bc27e37a501f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68302 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2022-10-20soc/intel/alderlake: Use `ufs.asl` from common code acpi blockSubrata Banik
This patch includes UFS ASL entry from common block ACPI code. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia77ea1c915d0dec991afa5b977af78487ae6a8b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68301 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2022-10-04soc/intel/alderlake: Fix UFS OCP fabric timeoutMeera Ravindranath
The delayed return of certain fetch instruction from memory to the UFS causes the OCP fabric to timeout on the transaction and become non-responsive. As recommended by the SoC and IP teams,program the OCP fabric register to avoid the timeout in the OCP fabric. This patch adds the following changes 1. Program the OCP fabric registers in the PS0 routine. 2. Move the ssdt contents of UFS to dsdt asl code to avoid duplication of UFS device creation BUG=b:240222922 TEST=Build and boot Nirwen UFS board, observe no system hang during Chrome PLT test. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-17soc/intel/alderlake/acpi: Changing USB ports indexing.Adam Mills
xhci.asl places the SS ports at 11-14, following HS ports 1-10. However, for Nissa, the kernel detects 12 HS ports 1-12 and 4 SS ports at 13-16, resulting in the PLD intended for SS ports 1 and 2 being associated with HS ports 11 and 12. Changing the asl for SS to 13-16 makes locations associate correctly and peering work. BUG=b:234544025 BRANCH=firmware-brya-14505.B TEST=manually verified on Nissa and Brya devices Change-Id: I57aef771a7ff086b71a9e90b81e1a3635f832b2f Signed-off-by: Adam Mills <adamjmills@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66590 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-23soc/intel/alderlake: Hide PMC and IOM devicesJeremy Soller
Hide these ACPI device so Windows does not warn about missing device drivers. Change-Id: Iba6cf7a17eefc9f4f247621f6625151f2fd5f3a7 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-07soc/intel/alderlake/acpi/gpio.asl: Add GPIO Commnity 3 for ADL-SMichał Żygowski
This patch fixes the issue with INTC1056 invalid resource reported by alderlake-pinctrl Linux driver on ADL-S platform. The driver also includes GPIO Community 3 in the GPIO list compared to ADL-N which was missing in GPIO ACPI device. TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A DDR4 WIFI and check there is no invalid resource error reported by alderlake-pinctrl Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I23da68c247de86438cc2eef2b5a5a9aa711c1d7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-07soc/intel/alderlake/acpi/gpio.asl: Fix lower case typoMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If66c2799d4d74ff9f309665a0336b5f679796f9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-28soc/intel/alderlake/acpi: Add ADL-S devicesMichał Żygowski
Add PCIe Root Ports, USB ports and SIO devices for ADL-S chipset. Add IRQ routing tables for PCIe Root ports up to 28th. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I508fa1396b07f38801bcf50cdfdc876356d7ae9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63785 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/alderlake: add GPIO definitions for PCH-SMichał Kopeć
Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles the split. Based on: - Intel PCH-S EDS Vol2 (#621483) - Alderlake-S FSP - slimbootloader sources - Linux alderlake-pinctrl driver Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-09soc/intel/alderlake: Add config option for S3 ACPISean Rhodes
Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust the ACPI to not offer D3Cold when using S3. This patch is the Alder Lake equivalent of CB:59024. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-03-17soc/intel/adl: Remove IOM Mctp command from TCSS ASLMAULIK V VAGHELA
TCSS ASL code was carried forward from TGL and it used to follow the same sequence. Recently as part of s0ix hang issue, it was found that sending IOM MCTP command as part of TCSS D3 Cold enter-exit sequence created an issue. We discovered that due to change in hardware sequence, ADL should not set/reset IOM MCTP during D3 cold entry or exit. This patch removes the bit setting from ASL file to prevent hang in the system. This patch also removes obsolete Pcode mailbox communication which is no longer required for ADL. BUG=b:220796339 BRANCH=firmware-brya-14505.B TEST=Check if hang issue is resolved with the CL and no other regression observed Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62861 Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake NKrishna Prasad Bhat
Alder Lake N SOC has eMMC device. Add ACPI ASL methods for it. Change-Id: I53f04e81584493049d37b46e078d394d3c8a2f09 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-06soc/intel/alderlake: Add minimal ACPI support for PEG portsTim Wawrzynczak
Add minimal Device entries with just an _ADR for each of the PEG ports for P and M chipsets (N does not have any PEG ports). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2021-11-17Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"Maulik V Vaghela
This reverts commit 1399442289607acc5203fb12df64e9081b3c3aa4. Reason for revert: Some Cr50 chips with old firmware version (x.y.22) don't support long pulse interrupt command, requiring dynamic GPIO PM to be disabled to intercept short pulse interrupt. Due to this coreboot needs to expose SGPM, RGPM and EGPM ACPI methods to support power gating of GPIO communities from the kernel when dynamic GPIO PM is disabled. BUG=b:204832081 BRANCH=None Test= S0ix works with dynamic PM disabled. Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/58811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-29soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimizationJohn Zhao
The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency optimization. This change adds additional ACPI DSM function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the USB4/TBT topology which has the same implementation on Tiger Lake in commit I5a19118b75ed0a78b7436f2f90295c03928300d7. BUG=b:199757442 TEST= It was validated that the first connected device waits only 50ms instead of 100ms and all functions work on Alder Lake platform boards. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I0c8977c96de27ab0e554469eba658660975b8493 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-04soc/intel/adl: Drop SGPM, RGPM and EGPM methodsMeera Ravindranath
These methods can now be dropped as Dynamic GPIO PM is enabled. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0c7b67b5414d8c80775ab7678ce7b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-10soc/intel/alderlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch alderlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-01soc/intel/alderlake: Fix processor hang while plug unplug of TBT deviceSugnan Prabhu S
Processor hang is observed while hot plug unplug of TBT device. BIOS should execute TBT PCIe RP RTD3 flow based on the value of TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if BIT30 in TBT FW version is not set. BUG=b:194880254 Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56503 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-20soc/intel/alderlake: Add support for I2C6 and I2C7Varshit B Pandya
As per the EDS revision 1.3 add support for I2C6 and I2C7. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id918d55e48b91993af9de8381995917aef55edc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29soc/intel/alderlake: Enable support for common IRQ blockTim Wawrzynczak
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows ADL boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. BUG=b:176858827 TEST=brya0, grep 'IO-APIC' /proc/interrupts (compressed to fit) 0: 36 0 0 0 0 0 0 0 IO-APIC 2-edge time 1: 0 0 9 0 0 0 0 0 IO-APIC 1-edge i804 8: 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 21705 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC 18: 0 0 0 0 0 0 0 0 IO-APIC 18-fasteoi inte 20: 0 0 0 0 0 0 0 394 IO-APIC 20-fasteoi idma 23: 2280 0 0 0 0 0 0 0 IO-APIC 23-fasteoi idma 26: 0 0 26 0 0 0 0 0 IO-APIC 26-fasteoi idma 27: 0 0 0 6 0 0 0 0 IO-APIC 27-fasteoi idma 28: 0 0 0 0 0 0 0 0 IO-APIC 28-fasteoi idma 29: 0 0 0 0 25784 0 0 0 IO-APIC 29-fasteoi idma 30: 0 0 0 0 0 0 0 0 IO-APIC 30-fasteoi idma 31: 0 0 0 0 0 0 226 0 IO-APIC 31-fasteoi idma 77: 0 0 0 0 0 2604 0 0 IO-APIC 77-edge cr50 100: 0 0 0 0 0 0 0 0 IO-APIC 100-fasteoi ELAN 103: 0 0 0 0 0 0 0 0 IO-APIC 103-fasteoi chro abbreviated _PRT dump: If (PICM) Package (){0x0002FFFF, 0, 0, 0x10}, Package (){0x0004FFFF, 0, 0, 0x11}, Package (){0x0005FFFF, 0, 0, 0x12}, Package (){0x0006FFFF, 0, 0, 0x13}, Package (){0x0006FFFF, 1, 0, 0x14}, Package (){0x0007FFFF, 0, 0, 0x15}, Package (){0x0007FFFF, 1, 0, 0x16}, Package (){0x0007FFFF, 2, 0, 0x17}, Package (){0x0007FFFF, 3, 0, 0x10}, Package (){0x000DFFFF, 0, 0, 0x11}, Package (){0x0012FFFF, 0, 0, 0x18}, Package (){0x0012FFFF, 1, 0, 0x19}, Package (){0x0014FFFF, 0, 0, 0x12}, Package (){0x0014FFFF, 1, 0, 0x13}, Package (){0x0015FFFF, 0, 0, 0x1A}, Package (){0x0015FFFF, 1, 0, 0x1B}, Package (){0x0015FFFF, 2, 0, 0x1C}, Package (){0x0015FFFF, 3, 0, 0x1D}, Package (){0x0016FFFF, 0, 0, 0x14}, Package (){0x0016FFFF, 1, 0, 0x15}, Package (){0x0016FFFF, 2, 0, 0x16}, Package (){0x0016FFFF, 3, 0, 0x17}, Package (){0x0017FFFF, 0, 0, 0x10}, Package (){0x0019FFFF, 0, 0, 0x1E}, Package (){0x0019FFFF, 1, 0, 0x1F}, Package (){0x0019FFFF, 2, 0, 0x20}, Package (){0x001CFFFF, 0, 0, 0x10}, Package (){0x001CFFFF, 1, 0, 0x11}, Package (){0x001CFFFF, 2, 0, 0x12}, Package (){0x001CFFFF, 3, 0, 0x13}, Package (){0x001DFFFF, 0, 0, 0x10}, Package (){0x001DFFFF, 1, 0, 0x11}, Package (){0x001DFFFF, 2, 0, 0x12}, Package (){0x001DFFFF, 3, 0, 0x13}, Package (){0x001EFFFF, 0, 0, 0x14}, Package (){0x001EFFFF, 1, 0, 0x15}, Package (){0x001EFFFF, 2, 0, 0x16}, Package (){0x001EFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 1, 0, 0x15}, Package (){0x001FFFFF, 2, 0, 0x16}, Package (){0x001FFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 0, 0, 0x14}, Else Package (){0x0002FFFF, 0, 0, 0x0B}, Package (){0x0004FFFF, 0, 0, 0x0A}, Package (){0x0005FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 0, 0, 0x0B}, Package (){0x0007FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 2, 0, 0x0B}, Package (){0x0007FFFF, 3, 0, 0x0B}, Package (){0x000DFFFF, 0, 0, 0x0A}, Package (){0x0014FFFF, 0, 0, 0x0B}, Package (){0x0014FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 0, 0, 0x0B}, Package (){0x0016FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 2, 0, 0x0B}, Package (){0x0016FFFF, 3, 0, 0x0B}, Package (){0x0017FFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 1, 0, 0x0A}, Package (){0x001CFFFF, 2, 0, 0x0B}, Package (){0x001CFFFF, 3, 0, 0x0B}, Package (){0x001DFFFF, 0, 0, 0x0B}, Package (){0x001DFFFF, 1, 0, 0x0A}, Package (){0x001DFFFF, 2, 0, 0x0B}, Package (){0x001DFFFF, 3, 0, 0x0B}, Package (){0x001EFFFF, 0, 0, 0x0B}, Package (){0x001EFFFF, 1, 0, 0x0B}, Package (){0x001EFFFF, 2, 0, 0x0B}, Package (){0x001EFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 1, 0, 0x0B}, Package (){0x001FFFFF, 2, 0, 0x0B}, Package (){0x001FFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 0, 0, 0x0B}, dmesg shows no GSI or PCI errors, TPM & touchpad IRQs still work Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1e7a708183ac4170b28da9565137fa2f5088a7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/54683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07soc/intel/alderlake: Update ACPI device ID of IOMMaulik V Vaghela
ACPI device ID of IOM device has been changed for Alder Lake. Updating it to make it compatible with kernel TEST=ACPI ID is updated and kernel driver works as expected Cq-Depend: chromium:2936144 Change-Id: Ifdfcd0c1534e8204719e59e718688cd42e846e84 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.aslMaulik V Vaghela
We were not adding power management handling of GPIO_COM3 in gpio.asl This can affect s0ix flow where platform won't go into s0ix since GPIO_COM3 is not power gated. BUG=b:188392183 BRANCH=None TEST=Platform should enter to s0ix and GPIO COMM3 should not block an entry to s0ix. Change-Id: I3f269c66bdd6337adb0d2bd29d0b7d72ced19ec4 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-10soc/intel/alderlake: Skip D3Cold for TBTSubrata Banik
Check TBT NVM FW Ready (INFR) bit to skip D3Cold for TBT when device is in disconnected state. Not adhering this recommendation is blocking the S0ix state transition. BUG=b:183670327 TEST=S0ix state transition occurs with TBT disconnected. Change-Id: Ib9b9ceee4393aeba37fdcb4e05d1b279a6ff72d2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-06soc/intel/alderlake: Update variable SD3C to only track enabled devicesJohn Zhao
Each TCSS DMA is grouped together with two PCIe RPs in terms of PM flow. This change ensures that SD3C is updated for the TCSS DMA devices corresponding to the TBT RP ports. If TBT port is 0 or 1, SD3C for DMA0 is updated, else for DMA1. BUG=None TEST=Built Alderlake image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia3462dfbb287a374960a57bb4c3541db2a435611 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51965 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06soc/intel/alderlake: Remove TCSS DMA _DSM methodJohn Zhao
The kernel does not need TCSS DMA's _DSM method. This change simply removes this method. BUG=None TEST=Built Alderlake image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I313f9c8913bb8cf54581c5460ac3fb1597291ad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik
Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15soc/intel/alderlake: Drop 100ms delay and do not poll Link ActiveJohn Zhao
Drop the 100ms delay in the _PS0 method because kernel already adds this 100ms. This change also drops polling TBT PCIe root ports Link Active State because this scheme is not applicable for SW CM. BUG=None TEST=Built Alderlake coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/alderlake: Remove _DSD from tcss_pciexp ASL fileTim Wawrzynczak
The _DSD is generated at runtime using the Intel common pcie driver, therefore remove it from the ASL files. BUG=b:182522802, b:182478306 TEST=boot into latest kernel, no thunderbolt driver errors seen Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iee25a77bf5cc6636f46a5c32f3eeabe8524e0a04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51454 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/alderlake: Remove _DSD from tcss_dma ASL fileTim Wawrzynczak
The _DSD is generated at runtime using the Intel common USB4 driver, therefore remove it from the ASL files. BUG=b:182522802, b:182478306 TEST=boot into latest kernel, no thunderbolt driver errors seen Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I77dc283aeb5f52191255137e941487cf68cb7970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51453 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Include gfx.asl from northbridgeAngel Pons
The iGPU is on the northbridge or system agent, not the southbridge. Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-17soc/intel/alderlake: Fix PCI IRQ tablesTim Wawrzynczak
Both the IO-APIC and PIC mode PCI IRQ tables are incorrect for ADL; the 2nd field in each package is supposed to be pin, not function number, and some of the IRQ #s differ from what the FSP programs, therefore align the ACPI table to match what the FSP is currently programming. BUG=b:180105941 TEST=boot brya, no more `GSI INT` or `failed to derive IRQ routing` errors seen in dmesg Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I182be69e8d9ebd854ed74dbb69f4d1f1a539cf2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-30soc/intel/common: Move gfx.asl to drivers/intel/gmaMatt DeVillier
Adjust platform-level includes as needed. Change-Id: I376349ccddb95c166f0836ec1273bb8252c7c155 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-20soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPDMichael Niewöhner
Replace the two obsolete LPID implementations with the new PEPD device. The PEPD device gets included in the plaforms' `southbridge.asl`, since it is required to load the `intel_pmc_core` module in Linux, which checks for the _HID. (See CB:46469 for more info on that.) There is no harm for mainboards not supporting S0ix, because the _DSM function won't be called with the LPS0 UUID on such boards. Such boards can use the debugging functionality of `intel_pmc_core`, too. Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/intel: Make use of common gfx.aslSubrata Banik
Add gfx.asl file for all IA SOCs to allow for graphics-related ACPI devices and methods. TEST=Able to build and boot TGL platform Dump and disassemble DSDT, verify GFX0 device present as below Device (GFX0) { Name (_ADR, 0x00020000) // _ADR: Address } Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/alderlake/acpi: Add SoC ACPI directory for ADLSubrata Banik
List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake up from sleep states. 3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH, LAN, HDA etc. Change-Id: I7509e8c46038b1edfc501db74e763f198efb56ab Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27soc/intel/alderlake: Add GPIOs for Alder Lake SOCSubrata Banik
Add definitions for the GPIO pins on Alder Lake LP, as well as GPIO IRQ routing information and supporting ACPI ASL. For now, add the following 5 GPIO communities and 13 GPIO groups: Comm. 0: GPP_B, GPP_T, GPP_A Comm. 1: GPP_S, GPP_H, GPP_D Comm. 2: GPD Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS Comm. 5: GPP_R, GPP_SPI0 Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 20:30:44 +0000