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path: root/src/soc/intel/alderlake/acpi.c
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2022-12-07soc/intel: Set IO APIC DMAR entry based on hwArthur Heymans
This avoids the need to hardcode the IOAPIC ID. Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70268 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-02soc/intel/alderlake: skip external buses for D-states listEran Mitrani
The devices in the list that was introduced in commit c66ea985776 ("soc/intel/alderlake: provide a list of D-states to enter LPM") are all internal. This CL skips the external buses (which caused the addition of packages to non-existant paths such as "_SB.PCI0.RP1.MCHC", and warnings from the kernel) BUG=b:231582182 TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-29soc/intel/alderlake/acpi.c: Don't look up coreboot CPU indexArthur Heymans
The coreboot CPU index for a lapic is arbitrary: it depends on which CPU obtains a spinlock first. Simply using an increasing index will result in consistent ACPI tables across each boot. Change-Id: Iaaaef213b32b33e3ec9f4874d576896c2335211c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69510 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-16soc/intel/*: Use SSDT to pass A4GB and A4GSArthur Heymans
GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-15soc/intel/alderlake: Move array declarationArthur Heymans
Clang does not like array declarations inside plain switch cases. There are 2 options to fix this: use a block inside the switch statement, or declare it outside the switch statement. This does the latter. Change-Id: I9a02136fd63ac171b2bec4647c30c7eece930246 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-14soc/intel/alderlake: Fix Coverity CID 1488814Tarun Tuli
CID 1488814:  Uninitialized variables  (UNINIT) Commit c66ea98 introduced an issue after static analysis on merge. Because every APIC is associated with a CPU, this did not result in any issues at runtime but should be fixed/cleaned up. Now, the path name is initialized to null. Fixes: Coverity CID 1488814, commit c66ea98 TEST=Built on brya Change-Id: I0cfc8fd7a0c39e6610a9361630e3755293084f3d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-12soc/intel/alderlake: provide a list of D-states to enter LPMTarun Tuli
Implement sub-function 1 (Get Device Constraints) of the Low Power S0 Idle Device-Specific Method (_DSM). This provides a way in which to describe various devices required D-states to enter LPM (S0ix). The information can be used to help in diagnostics and understanding of S0ix entry failure. Values were derived from Intel document 595644 (rev 0.45) and the ADL FSP sample ASL. This implementation adds support for ADL. Other SoC's could be ported to be included as well. If they aren't, they will default to the existing behavior of a single hardcoded device to ensure compatibility with Windows. TEST=Built and tested on brya by verifying SSDT contents Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
2022-01-05soc/intel: Remove unused <string.h>Elyes HAOUAS
Found using following command: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy(\|memmove(\|memset(\|memcmp(\|memchr(\|strdup(\|strconcat(\|strnlen(\|strlen(\|strchr(\|strncpy(\|strcpy(\|strcmp(\|strncmp(\|strspn(\|strcspn(\|strstr(\|strtok_r(\|strtok(\|atol(\|strrchr(\|skip_atoi(\|vsnprintf(\|snprintf(' -- src/) Change-Id: Iae90ff482f534d8de2a519619c20a019d054e700 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19soc/intel: Constify `soc_get_cstate_map()`Angel Pons
Return a read-only pointer from the `soc_get_cstate_map()` function. Also, constify the actual data where applicable. Change-Id: I7d46f1e373971c789eaf1eb582e9aa2d3f661785 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-19soc/intel/*/acpi.c: Don't copy structs with `memcpy()`Angel Pons
A regular assignment works just as well and also allows type-checking. Change-Id: Id772771f000ba3bad5d4af05f5651c0f0ee43d6d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-17soc/intel: deduplicate acpi_fill_soc_wakeMichael Niewöhner
The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in common code. Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-28soc/intel: Drop casts around `soc_read_pmc_base()`Angel Pons
The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then casted to a pointer type for use with `read32()` and/or `write32()`. But since commit b324df6a540d154cc9267c0398654f9142aae052 (arch/x86: Provide readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()` functions live in `arch/mmio.h`. These functions use the `uintptr_t type for the address parameter instead of a pointer type, and using them with the `soc_read_pmc_base()` function allows dropping the casts to pointer. Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-06-25soc/intel/alderlake: Update s0ix cstate tableBernardo Perez Priego
Cstate C7 is not supported in ADL, replacing this unsupported state with C6 in the s0ix cstate table. BUG=None TEST=Boot device to OS. Print supported CStates and latencies. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I471f71481d337e3fafa4acab7fe8a39677c8710c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55734 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16soc/intel/alderlake: Make use of is_devfn_enabled() functionSubrata Banik
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on ADL. Change-Id: I92671992ec14fd2adca1635b0791ac8b456332e9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55292 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/alderlake: Use device ID from pci_devs header fileJohn Zhao
This change applies device ID from the SoC pci_devs.h directly. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ic5d2910ca53c02527aef0ad33ed52a35f2bdf7af Reviewed-on: https://review.coreboot.org/c/coreboot/+/52640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26soc/intel/alderlake: Fix devices list in the DMAR DRHD structureJohn Zhao
The VT-d specification states that device scope for remapping hardware unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list of hardware unit definition structure. This change fixes the devices list in the DMAR DRHD structure. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I14c34ad66a5ee8c30acabd8fe5a05c22087f9120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out identical acpigen GPIO helpersAngel Pons
Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16ACPI: Add acpi_reset_gnvs_for_wake()Kyösti Mälkki
With chipset_power_state filled in romstage CBMEM hooks and GNVS allocated early in ramstage, GNVS wake source is now also filled for normal boot path. Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-08soc/intel: Drop CID1 from GNVSKyösti Mälkki
The only reference to CID1 is in common/acpi/wifi.asl and only two braswell boards include it. Everywhere else the value in GNVS was unused. Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-03src: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-26soc/intel: Move c-state resource defineMarc Jones
De-duplicate the MWAIT_RES define. Move it to intel/common/block. Change-Id: I43903e4f02a549f53101e79f6febd42f2e54f98f Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49802 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-20ACPI GNVS: Drop most dev_count_cpu()Kyösti Mälkki
Only amd/picasso and amd/stoneyridge have reference to PCNT and that could be replaced with acpigen. Remove the PCNT name from GNVS OperationRegion elsewhere. Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-10soc/intel: Rename to soc_fill_gnvs()Kyösti Mälkki
Replace acpi_create_gnvs() under soc/ to reflect their changed funcionality. Change-Id: I7bdbe0d6f795252e713e9785ada2b6320e6604b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48717 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant ChromeOS setup for GNVSKyösti Mälkki
Already done in common gnvs_get_or_create() implementation once gnvs_chromeos_ptr() is defined for platforms. Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant CONSOLE_CBMEM setup in GNVSKyösti Mälkki
Already done from common gnvs_get_or_create() implementation after gnvs_cbmc_ptr() is defined. Change-Id: I77c292cd9590d7fc54d8b21ea62717a2d77e5ba4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48702 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/alderlake/ramstage: Do initial SoC commit till ramstageSubrata Banik
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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