coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-11-23	soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE	Subrata Banik
2020-11-22	soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and ...	Bora Guvendik
2020-11-03	soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order	Subrata Banik
2020-11-02	soc/intel: Use of common reset code block	Subrata Banik
2020-10-21	soc/intel: convert XTAL frequency constant to Kconfig	Michael Niewöhner
2020-10-21	soc/intel/common: add Kconfig for PM Timer emulation support	Michael Niewöhner
2020-10-17	cpu/intel,soc/intel: drop Kconfig for hyperthreading	Michael Niewöhner
2020-10-14	soc/intel/alderlake: Enable TME for Alder Lake	Subrata Banik
2020-10-06	soc/intel/alderlake/acpi: Add SoC ACPI directory for ADL	Subrata Banik
2020-10-03	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	Subrata Banik
2020-10-02	drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config	Shelley Chen
2020-09-24	soc/intel/alderlake: Select ACPI_INTEL_HARDWARE_SLEEP_VALUES	Angel Pons
2020-09-15	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	Subrata Banik
2020-09-09	vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332	Subrata Banik
2020-09-05	soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock	Subrata Banik