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path: root/src/soc/imgtec/pistachio
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2016-12-05spi: Define and use spi_ctrlr structureFurquan Shaikh
1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17684 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Pass pointer to spi_slave structure in spi_setup_slaveFurquan Shaikh
For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Fix parameter types for spi functionsFurquan Shaikh
1. Use size_t instead of unsigned int for bytes_out and bytes_in. 2. Use const attribute for spi_slave structure passed into xfer, claim bus and release bus functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22spi: Get rid of max_transfer_size parameter in spi_slave structureFurquan Shaikh
max_transfer_size is a property of the SPI controller and not of the spi slave. Also, this is used only on one SoC currently. There is no need to handle this at the spi flash layer. This change moves the handling of max_transfer_size to SoC SPI driver and gets rid of the max_transfer_size parameter. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: I19a1d0a83395a58c2bc1614b24518a3220945a60 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17463 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-09drivers/uart: Use uart_platform_refclk for all UART modelsLee Leahy
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-21imgtec/pistachio: Fix memlayout ASSERT with new binutilsStefan Reinauer
With binutils 2.26 our memlayout ASSERT for mirrored SRAM regions gets confused due to the lack of parentheses grouping the expressions. This fixes the following issue: LINK cbfs/fallback/bootblock.debug mipsel-elf-ld.bfd: bootblock and gram_bootblock do not match! mipsel-elf-ld.bfd: romstage and kseg0_romstage do not match! Change-Id: Ib406e229b8a552d9ffc4538b55ee0269bfed62a8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14440 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-02-22urara: Increase bootblock sizeJulius Werner
The urara bootblock is less than a kilobyte from its limit (20K). There's more than enough space available so increase it to avoid impeding changes to core code. Also add some more automated checks to better model the platform's multiple windows into the same memory region and guard against accidental overlaps by a seemingly benign change to one window. Change-Id: I2e535b56d5d1748830ea1e70fd12fd9e87009bce Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13733 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-12tegra132/pistachio: Increase romstage size in memlayout.ldJulius Werner
These SoCs have come within a kilobyte of their romstage limit, so let's expand that a little to make room for future core code contributions. (In the Tegra case just by copying the layout from Tegra210, because why not? Keeps things simple.) BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug and Urara. Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13668 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-31imgtec/pistachio: disable default RPU gate register valuesIonela Voinescu
The RPU Clock register defaults to on for all clocks. This is modified to OFF, and the MIPS clock control modified to ON, by default. This is because the linux kernel will manage the clocks at all times, but the RPU can only disable clocks if the WIFI module has been loaded. Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-31imgtec/pistachio: memlayout: update GRAM sizeIonela Voinescu
GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role of SRAM) was placed at a 4K aligned address, resulting in a size of 408KB. Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: I2C: fix base address for I2C clock setupIonela Voinescu
The base address for the I2C dividers (DIV1 and CLOCKOUT) was erroneously set to the toplevel clock controller base address and not to the correct peripherals clock controller base address. Change-Id: I66bbc1e741bcf6251babee7ddd6376d49d7cb3d1 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12771 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: identity map SOC registers regionIonela Voinescu
This region must be mapped uncached. This is necesary for an U-boot payload which will obtain all register base addresses as physical addresses from the device tree and will use them as such. Change-Id: Ib5041df7d90c6ef61b7448a18dd732afbd9489ca Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12770 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-31imgtec/pistachio: Add SOC_REGISTERS memory regionIonela Voinescu
When used with a U-boot payload it will need this region identity mapped also, so we're defining it in preparation for that functionality. Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12768 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: Use SYS PLL in integer modeIonela Voinescu
Use SYS PLL in integer mode by default to reduce jitter. DSMPD_MASK is defined and can be used to switch to fractional mode. Tested on pistachio bring up board. Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12767 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-29mips: add coherency argument to identity mappingIonela Voinescu
In order for a U-boot payload to work properly the soc_registers region (device registers) needs to be mapped as uncached. Therefore, add a coherency argument to the identity mapping funcion which will establish the type of mapping. Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-27mainboard/google/urara: change SYS PLL to 700MHzIonela Voinescu
This requires changes the interface that sets up the system PLL to support a given reference devider value and given feedback value. Also, this requires a change in the dividers used for UART, USB, I2C setup. Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12765 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-21imgtec/pistachio: DDR2, DDR3: DLL reset setIonela Voinescu
Bit 8 of the MR register is automatically set by the PHY during memory initilization but having it set in the register leads to a more clear understanding. Tested on Pistachio bring up board; DDR2 and DDR3 are initialized properly. Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12764 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-21imgtec/pistachio: DDR2, DDR3: DQS gate earlyIonela Voinescu
Switching on DQS Gate Early and DQS Gate Extension with 500R DQS/DSQN Resistors. This setup was recommended by Synopsys. Tested on Pistachio bring up board; DDR2 and DDR3 are initialized properly. Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12763 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-21imgtec/pistachio: increase CBFS cacheIonela Voinescu
Increase CBFS cache size to allow for a bigger payload. Change-Id: I47404ba9bbe95f6610189b971504019c0a1a81f0 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12762 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-17Drop src/cpu/ indirection for MIPSStefan Reinauer
Change-Id: I406166e650e07851ab1b293450fa29da8af075d9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12724 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17soc/imgtec/pistachio: add implementation for system resetIonela Voinescu
Implement system reset by calling the watchdog soft reset. Following the soft reset, the SoC will reset to the same logic state and therefore have the same effect as a hard (power-on) reset except for: - watchdog scratch registers will be unaffected (hard reset will clear them) - the real time clock will be unaffected BUG=none TEST=tested on Pistachio bring up board Change-Id: I1332c2249c756f6d8574fc5c407de52f88e60f08 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12755 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17soc/imgtec/pistachio: Implement hard_reset()Stefan Reinauer
Verified boot needs hard_reset() now, so offer a dummy implementation for the Imagination chip. Sorry, I don't have the specs for this chip anymore to make a real implementation, but I would like to keep this code from bit rotting. Change-Id: I15aa47f7d248b99901a2ac0e65a46b43d7718717 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12723 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-22linking: link bootblock.elf with .data and .bss sections againAaron Durbin
Currently coreboot expects the loader to clear the bss section for all stages. i.e. stages don't clear their own bss. On ARM SoCs the BootROM would be responsible for this. To do that one needs to include the bss section data (all zeros) in the bootblock.bin file. This was previously being attempted by keeping the .bss info in the .data section because objcopy happened zero out non-file allocated data section data. Instead go back to linking bootblock with the bss section but mark the bss section as loadable allocatable data. That way it will be included in the binary properly when objcopy -O binary is emplyed. Also do the same for the data section in the case of no non-zero object values are in the data section. Without this change the trick of including .bss in .data was not working when there wasn't a non-zero value object in the data section. BUG=None BRANCH=None TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains the cleared bss. Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09verstage: use common program.ld for linkingAaron Durbin
There's no reason to have a separate verstage.ld now that there is a unified stage linking strategy. Moreover verstage support is throughout the code base as it is so bring in those link script macros into the common memlayout.h as that removes one more specific thing a board/chipset needs to do in order to turn on verstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11516 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31imgtec/pistachio: remove timestamp_get() implementationAaron Durbin
As pistachio already provides timer_monotonic_get() let the generic timestamp_get() use that instead of having around another implementation of timestamp_get(). BUG=chrome-os-partner:44669 BRANCH=None TEST=None Change-Id: Iaa6db49f0055b7c2ef116f41453f838093e516e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11469 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-09imgtech/pistacho: Add vboot2 memory regionPatrick Georgi
Change-Id: I375397d4a1db6fef6b40421590f315c0f7eb0948 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11100 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: Icf83d5e2a3daea385af3572e9eac6b2431652c28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10640 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-21Remove old HAVE_UART_MEMORY_MAPPED select statementsMartin Roth
The HAVE_UART_MEMORY_MAPPED symbol is no longer present, so these don't actually select anything. Change-Id: I6d0eb610e48a4506ac7449ac677ee67981d0ff0d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10608 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-12pistachio: add DDR3 initialization codeIonela Voinescu
Initialization for the Winbond W631GG6KB part using Synopsys DDR uMCTL and DDR Phy. This code adds a separate function for DDR3 initialization and moves all the necessary defines in a separate header file. The programming procedure that is executed at power up to bring up the uMCTL, PHY and memories into a state where reads and writes to the memory can be performed is the following: 1. uPCTL (Universal DDR protocol controller) initialization The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH needed for driving the memory power-up sequence are programmed as a function of the internal timers clock frequency. Organization (memory chip specific) values are set (column/bank/row address width and number of ranks), together with other static values (latency, timing, power up configuration). All these values are static, provided by the datasheet, being determined by the memory type, size and frequency. 2. PHY initialization The PHY is programmed with datasheet provided values, specifying the initialization values for it to send to the external memory (timing parameters). Also, delay lines (DLL) and strength of drive pads are calibrated (based on external conditions: temperature, voltage, noise) and locked. After that, the PHY goes through a trainig process (also dependent on the current conditions at boot time) to establish precise timing configuration between the DDR clock and DQS (data strobe) and between DQS and DQ (data). 3. Memory power up 4. Switch from configuration state to access state. It was tested on Pistachio bring up board where DDR was initialized properly and ramstage executed correctly Change-Id: I3bcbce2044327a22fce09b184d85ee11228a6b2b Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10529 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-12pistachio: Use passive windowing as DQS gating schemeIonela Voinescu
Switching from active windowing DQS gating scheme to passive windowing mode resolves boot stability issues on chips found to have memory corruption issues during boot or memory tests. It was tested on Pistachio bring up board where DDR is initialized properly and ramstage executed correctly; We have cycled units over 12,000 times with no boot errors. This option was chosen over the alternative of using passive windowing mode for DQS training and after switching back to active mode, as this option was recommended by Synopsys. Using the alternative would give different timing values during training that were not longer accurate during normal activity. Change-Id: Ie604eddc0a9a982b2f89198f44deb88a01b7b322 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-10pistachio: sort included header filesIonela Voinescu
Place included header files in alphabetical order. Change-Id: Ice23178d1f07e2cb0178efbc7ce487d54bf3f708 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10459 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-10pistachio: initialize cbmem area to be emptyIonela Voinescu
Use cbmem_initialize_empty() after DDR configuration so that cbmem is always initialized from scratch on each boot. Change-Id: Ic9ca34867b26aab82cf3154280694b6fb61ee11f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10458 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-09pistachio: increase romstage sizeIonela Voinescu
This change is necessary to support future additions to romstage. Change-Id: Ibb69994847945c7adbafbf2bc677b33821df8146 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10457 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-02Revert "pistashio: bump up romstage size"Aaron Durbin
This reverts commit 701211a6e57a17ea861b4ad682dca7416fc9050e. Change-Id: Ib3e573548bff5c17ab30cfab3d833a2065d689c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10222 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-26pistashio: bump up romstage sizeAaron Durbin
Making large changes in pieces is leading to a little bloat. Bump up the romstage size temporarily so that jenkins will be happy. Change-Id: I6f9facb4ca488cf41741a3ed6d0ed7f66d4778b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10220 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19Remove Kconfig variable that has no effectPatrick Georgi
DYNAMIC_CBMEM is only selected a couple of times but never declared or read. Remove it. Change-Id: I5016dac2c935d3f261001e9f388a8989540e93ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-07imgtec/pistachio: Add comment on the unusual memory layoutPatrick Georgi
To avoid having to dig up the constraints again, document the memory layout right in memlayout.ld. Change-Id: I298cc880ae462f5b197ab2f64beb2f0e0d9f5a7d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10039 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30imgtech/pistachio: Give some more space to the bootblockPatrick Georgi
The memory layout isn't very clear here, since there are two regions (bootblock and "SRAM") that are actually the same. So when increasing the bootblock's size, we also need to move the romstage around. Change-Id: Ib158a4ef96b7c1dd1132b6e8bd47a0eb9c3951d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10035 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-04-29kbuild: automatically include SOCsStefan Reinauer
This change switches all SOC vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in soc/Makefile.inc or in soc/<vendor>/Makefile.inc. This means, vendor and SOC directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: Iede26fe184b09c53cec23a545d04953701cbc41d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9799 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22imgtec/pistachio: DDR reads return to controller with no bubblesIonela Voinescu
When the PHY is compiled to run in HDR(half data rate), then either NOBUB or FXDAT must be set to 1 in the DDR system general configuration register. NOBUB specifies that reads should be returned to the controller with no bubbles and this is felt preferable to the fixed latency option (FXDAT). Both of them inrease read latency. BRANCH=none BUG=chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly Change-Id: Iee530ba5bb0acc889fba447dc2ee5cb965ba6926 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7944b4af45d9504098f8b4af44d0f5abafea42c Original-Change-Id: I9ced76bd670fc4efa7441d57e15f97871b046ae9 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264341 Original-Reviewed-by: James Hartley <james.hartley@imgtec.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9917 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22imgtec/pistachio: DDR row/bank/column mappingIonela Voinescu
The DRAM configuration register, apart from holding the device density and width also has a rudimentary address mapping scheme. Currently this is set to the default Bank/Row/Column. This means that the memory is segmented into 8 chunks, each with a page detector. If all the activity is in one section of memory then the other 7 page detectors could be idle. Changing this to Row/Bank/Column would concatenate the page detectors meaning that all 8 could be used by a single initiator. This may not gain anything in a synthetic bandwidth test but could yield extra performance in a real world application or benchmark. BRANCH=none BUG=chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly; all access to DDR works properly in Coreboot ramstage, Depthcharge and Linux; no performance tests were ran so far. Change-Id: I22d86bf3b679ed63884d7436d9d7bbaf1726f640 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e852ed42afcdc2062a0037144bab723227cb1f1f Original-Change-Id: If90b0cf5ce86db5e3d6d362873d22d4269e3a49f Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264340 Original-Reviewed-by: James Hartley <james.hartley@imgtec.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9916 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22soc: select generic gpio lib on (almost) all non-x86 SOCsStefan Reinauer
BOARD_ID functionality is not what requires the GPIO lib, but it is the mainboard specific implementations that do. The option essentially says whether the SoC provides <soc/gpio.h> (with the interface required by the common GPIO code). Right now, x86 and Samsung's Exynos SOCs don't have support for this interface. So this should be selected by the SOC, not by BOARD_ID_SUPPORT. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=none BRANCH=none TEST=emerge-storm coreboot still successfully compiled an image Change-Id: I0ce2bd7ce023f22791d31a6245833b61135504b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0dd4dea521372194eedf11b077d95fd3b15ad9f7 Original-Change-Id: I3dea6c2fb42a23fcb9d384c3bbfa7fc8e217be2d Original-Reviewed-on: https://chromium-review.googlesource.com/262743 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9899 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22imgtec/pistachio: increase RAM CBFS cache sizeVadim Bendebury
CBFS cache use is very close to the limit, does not allow to read much more from CBFS. BRANCH=none BUG=chrome-os-partner:36586 TEST=the upcoming patches do not fail due to the lack of room in CBFS cache any more Change-Id: I8e784891e59ca284b3bd82557c2114a2f450d8a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c94d55c8042db81c1eb0c10d5f24883e00cdc19a Original-Change-Id: Ic09dbd5b4a0e165ccef396ff8a9e21b12c49b705 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263268 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: Remove 50% DDR bandwidth restrictionIonela Voinescu
The existing DDR setup configures the burst length to be 8. However the DDR controller can only be given sufficient data per clock to satisfy a burst length of 4, hence the bursts are only half populated. This results in a 50% drop of efficiency. Fix this by configuring the burst size to 4. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly BRANCH=none Change-Id: I761ba73a04688841ca39a370b7cb99b6e0b22964 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0e590ab8387dbbccef45dc84d1eeafee2abc9e2e Original-Change-Id: I585385b65e330624ad70292349e50c6695eeeb6c Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256305 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9847 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: Decrease DDR ODT from 75R to 50RIonela Voinescu
The DDR On Die Termination was incorrectly configured at 75R, where as the data sheet suggests for DDR2-800 it should be set to 50R. Correct this by adjusting the ODT setting in the EMR register. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly BRANCH=none Change-Id: I2f0242c422b1cb3d1f64ce3dd17b62fef5e7e155 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ac081ac59c0dc3d16a7b540cd379fb870b6cfe40 Original-Change-Id: If7951812033c4e88f4be3c143fb49526eddba142 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256304 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9846 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: clean DDR2 initialization codeIonela Voinescu
The proper way to initialize DDR2 is for the PHY to automatically establish precise timing configuration through the training process. The alternative (used initially for testing) is no longer needed. This change determined the removal of some local variables as they ended up being used in one location only. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly. BRANCH=none Change-Id: I31e9a8975d176a04061f9c84fe06cce850bb53b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e28f3ef9a22436bb0fa949df6f5a5c6a67002dfd Original-Change-Id: Ifb9c1bb6e0b71af72340381bd2349850d1b4af2d Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256303 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9845 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: add clock setup for all I2C interfacesIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; all I2C interfaces were tested with the TPM and they all work properly. BRANCH=none Change-Id: I02202585140beb818212c02800f6b7e4966a922a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 33b2adecc4939ac73fffba47adf1c8306a888b8d Original-Change-Id: Ida7eaa72d4d6e6b034319086410de5baa63788bc Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256361 Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21urara: Identity map DRAM/SRAMAndrew Bresticker
Using identity_map(), map the DRAM/SRAM regions to themselves (which happens to be using KUSEG on urara). The bootblock (which still runs in KSEG0) sets up the identity mapping in bootblock_mmu_init() so that ROM/RAM stages can be loaded into the KUSEG address range. The stack and pre-RAM CBMEM console also remain in KSEG0 since we don't really care about their physical addresses. Also splitting CBFS cache to pre and post RAM, to allow for larger rambase images. BUG=chrome-os-partner:36258 BRANCH=none TEST=With the rest of coreboot and depthcharge patches applied: - booted urara into the kernel login prompt - from depthcharge CLI tried accessing memory below 0x100000 - observed the exception. Change-Id: If78f1c5c54d3587fe83e25c79698b2e9e41d3309 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9668b440b35805e8ce442be62f67053cedcb205e Original-Change-Id: I187d02fa2ace08b9fb7a333c928e92c54465abc2 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246694 Reviewed-on: http://review.coreboot.org/9816 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21imgtec/pistachio: Add spi_crop_chunk()Patrick Georgi
This was added in upstream but not in Chromium OS where pistachio support was developed. Change-Id: I54f883776f19aa7bd357841731166e92d03145d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9808 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17pistachio: Move console UART to a Kconfig variableDavid Hendricks
This allows us to define the serial console UART on a per-board basis. BUG=chrome-os-partner:31438 BRANCH=none TEST=built and booted on urara w/ follow-up patches Change-Id: Idbb0d39bf8855df4312f7499c60b8b92826fdd07 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ed4cfdd5ed6ccbf87a50f56d3e07f2f1a9d49464 Original-Change-Id: I3faeb92f026062cded390603a610e5b8f7c9bc12 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243211 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/9777 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-04-17pistachio: add DDR2 initialization codeIonela Voinescu
This is the intialization code specific to the Winbond W972GG6JB-25 part using Synopsys DDR uMCTL and DDR Phy. This is DDR2 initialization code only (currently present on the bring up board). DDR3 initialization code will follow for boards having DDR3 memory. The programming procedure that is executed at power up to bring up the uMCTL, PHY and memories into a state where reads and writes to the memory can be performed is the following: 1. uPCTL (Universal DDR protocol controller) initialization The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH needed for driving the memory power-up sequence are programmed as a function of the internal timers clock frequency. Organization (memory chip specific) values are set (column/bank/row address width and number of ranks), together with other static values (latency, timing, power up configuration). All these values are static, provided by the datasheet, being determined by the memory type, size and frequency. 2. PHY initialization The PHY is programmed with datasheet provided values, specifying the initialization values for it to send to the external memory (timing parameters). Also, delay lines (DLL) and strength of drive pads are calibrated (based on external conditions: temperature, voltage, noise) and locked. After that, the PHY goes through a trainig process (also dependent on the current conditions at boot time) to establish precise timing configuration between the DDR clock and DQS (data strobe) and between DQS and DQ (data). 3. Memory power up 4. Switch from configuration state to access state. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly DDR2 is also tested during chip sort. Corner cases (performace of DDR in different conditions) will be tested after the chip reaches a stable state. BRANCH=none Change-Id: I0093dc175d064aad03052d5281679b008c1bf012 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3d0bacea0fd5bd3b12008b47e80de8398f447785 Original-Change-Id: I8437db6c84d77c4c51a3ee2b09cd3d14913c0d16 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241424 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9769 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17pistachio: report UART register widthVadim Bendebury
Pistachio UART closely matches 8250, the only difference is that its register file is mapped to a 32 bit bus. Provide a function to report register with so that the Coreboot table entry gets correct value. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: Icd72b115b4f339800d6c8b210a6617398232f806 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e1dc4156949b20efafbca2c19ff424436a400087 Original-Change-Id: Icafb014af338e05bbf1044b791683733685ffab3 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240028 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9740 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17uart: pass register width in the coreboot tableVadim Bendebury
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I30b742146069450941164afb04641b967a214d6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9738 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14pistachio: implement clock setup for I2C0Ionela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; I2C0 clock is set up properly. BRANCH=none Change-Id: I15ffc5f7d8e8aadfc3cd249284bc492d0d13d9a1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6404ab6ad12ea1579eaf5ae55a9eddd9bd9f96e2 Original-Change-Id: Iafdf492291b47f0088f3b5e621d630b8d21ab106 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250450 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9673 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14pistachio: Fix ROM clock base addressIonela Voinescu
The base address used was TOP CLOCK control address instead of the PERIPH CLOCK CONTROL. That was incorrect and is fixed with the current patch. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; now the hash accelerator, fed by this clock, is correctly clocked at 200MHz. BRANCH=none Change-Id: I0ead3951dc1dfc872881b8d1ae9b63f8104af50d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 871cb50ca43a6c760f346eb447e8ff102d8ca0b6 Original-Change-Id: I198d64f97a85a6fcf00c3853bf23d2d767e0e631 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245313 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9670 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14urara: add clock setup for MIPS CPU, ROM and EthernetIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works properly BRANCH=none Change-Id: Ie386d6af9eeba7a72b1b88d515e6cb1821569c6b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d4b8d8b6f965296f9ecf62da8e5f383c3667b077 Original-Change-Id: I9eb464340b0475ae735ba5573ab0841dac0d74eb Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/243215 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9669 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14pistachio: fix clocks setup codeIonela Voinescu
Some of the asserts were not done properly: the value has to be shifted before is matched with the mask. Added condition to exit while loop for USB clock setup. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; after this patch is applied none of the asserts fail and the code is executed properly. BRANCH=none Change-Id: Ib3aae9f7751a9f077bc95b6e0f9d63e3e16d8e4b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 96999a4322ba98e87bc6746ad05b30cc56704e2e Original-Change-Id: I8d2d468d618ca1ffcb1421409122482444e6d420 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/243214 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9667 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14pistachio: Use 1.8433179 MHz for UART refclkDavid Hendricks
BUG=chrome-os-partner:31438 BRANCH=none TEST=built and booted on urara w/ follow-up patches Change-Id: I3b03ce937e68539343e58b01e3bb714dd1f8c2dd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9493c57a14c8ab074baac1c065c6f39050dd9b2f Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I8e50c99913ea155ba0d5699f4789c1fe38b46808 Original-Reviewed-on: https://chromium-review.googlesource.com/243210 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/9666 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14pistachio: increase size of bootblock to 18 KBIonela Voinescu
With the added code for clock and MFIOs setup, bootblock now exceeds 16KB. This patch increases the allowed limit to 18KB. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works as expected BRANCH=none Change-Id: I166f882bd3db446bcd6f9e1f828cab22266c6ac7 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: da95db5ed348419b7905dc1ab68fd64d7b2eb5e0 Original-Change-Id: I0cacc6163f21ae3673c2716b12dde66bd48290f9 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/243213 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9665 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14pistachio: change memory layout as to allow bigger CBFS cacheIonela Voinescu
As the payload increases in size, a bigger CBFS cache is required. Therfore, bootblock, romstage and the cbfs cache were placed in GRAM (128 K) and the stack and cbmem console were moved to SRAM (64 K). With the exception of CBFS cache, the sizes of all the other regions remains the same. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA and bring up board; behavior was as expected. BRANCH=none Change-Id: I19857f785ca1514f7483d582c7ad6ee470a8fefc Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c895660dbdcd113bdc9d832beab30886313c28d6 Original-Change-Id: I004f8f081d04f83e3f5cee969e50803685cfdf67 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/236551 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9664 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14pistachio: spi: use same clock edge for RX and TXIonela Voinescu
When using this mode data is received and transmitted on the same edge of the SPFI clock, which allows for higher frequencies of operation. In this mode the maximum supported frequency is 50Mhz. If this mode is not enabled the maximum supported frequency is 25Mhz. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; the SPFI hardware block is fed by the system clock (with a fixed freqency of 400 MHz). To achieve the SPFI frequency of 50MHz the internal divider of SPFI must be set to 64. To achieve a frequency of 25 Mhz the internal divider must be set to 32. A value of 64 = division by 8 A value of 32 = division by 16 BRANCH=none Change-Id: Ifd5f739b6157b99e4c1f92b5bb72615ee610ae6c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8b6cce616ec7926682d4eff096563acf1dfd6c65 Original-Change-Id: I337b6fcf462bcf6021ca77a8b1133cf49140ba76 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241425 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14urara: Configure clocks and MFIOsIonela Voinescu
Set elements: - UART1 clock dividers and MFIOs - SPIM1 clock dividers and MFIOs - USB clock dividers - System clock divider - System PLL - MIPS CPU PLL BUG=chrome-os-partner:31438 TEST=tested on Pisachio bring up board; UART, SPI NOR, SPI NAND, and USB have proper functionality. BRANCH=none Change-Id: Ib01186a652fd59295a4cafc3ca99b94aa9564f74 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 65e68d82f34bb40ef3cfb397ecf5df0c83201151 Original-Change-Id: Ia2c31bbbfc020dc4fd71c72b877414adfdfc42a8 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241423 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14CBFS: Automate ROM image layout and remove hardcoded offsetsJulius Werner
Non-x86 boards currently need to hardcode the position of their CBFS master header in a Kconfig. This is very brittle because it is usually put in between the bootblock and the first CBFS entry, without any checks to guarantee that it won't overlap either of those. It is not fun to debug random failures that move and disappear with tiny alignment changes because someone decided to write "ORBC1112" over some part of your data section (in a way that is not visible in the symbolized .elf binaries, only in the final image). This patch seeks to prevent those issues and reduce the need for manual configuration by making the image layout a completely automated part of cbfstool. Since automated placement of the CBFS header means we can no longer hardcode its position into coreboot, this patch takes the existing x86 solution of placing a pointer to the header at the very end of the CBFS-managed section of the ROM and generalizes it to all architectures. This is now even possible with the read-only/read-write split in ChromeOS, since coreboot knows how large that section is from the CBFS_SIZE Kconfig (which is by default equal to ROM_SIZE, but can be changed on systems that place other data next to coreboot/CBFS in ROM). Also adds a feature to cbfstool that makes the -B (bootblock file name) argument on image creation optional, since we have recently found valid use cases for CBFS images that are not the first boot medium of the device (instead opened by an earlier bootloader that can already interpret CBFS) and therefore don't really need a bootblock. BRANCH=None BUG=None TEST=Built and booted on Veyron_Pinky, Nyan_Blaze and Falco. Change-Id: Ib715bb8db258e602991b34f994750a2d3e2d5adf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e9879c0fbd57f105254c54bacb3e592acdcad35c Original-Change-Id: Ifcc755326832755cfbccd6f0a12104cba28a20af Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229975 Reviewed-on: http://review.coreboot.org/9620 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-13spi: support controllers with limited transfer size capabilitiesVadim Bendebury
Some SPI controllers (like Imgtec Pistachio), have a hard limit on SPI read and write transactions. Limiting transfer size in the wrapper allows to provide the API user with unlimited transfer size transactions. The tranfer size limitation is added to the spi_slave structure, which is set up by the controller driver. The value of zero in this field means 'unlimited transfer size'. It will work with existion drivers, as they all either keep structures in the bss segment, or initialize them to all zeros. This patch addresses the problem for reads only, as coreboot is not expected to require to write long chunks into SPI devices. BRANCH=none BUG=chrome-os-partner:32441, chrome-os-partner:31438 TEST=set transfer size limit to artificially low value (4K) and observed proper operation on both Pistachio and ipq8086: both Storm and Urara booted through romstage and ramstage. Change-Id: Ibb96aa499c3eec458c94bf1193fbbbf5f54e1477 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4f064fdca5b6c214e7a7f2751dc24e33cac2ea45 Original-Change-Id: I9df24f302edc872bed991ea450c0af33a1c0ff7b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232239 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9571 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13urara: add support for DMA coherent memory areaIonela Voinescu
The information about the DMA memory area is further passed through the coreboot table to the payload. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA; DMA memory area was used to test the functionality of the DWC2 USB controller driver; behavior was as expected. BRANCH=none Change-Id: I658e32352bd5fab493ffe15ad9340e19d02fd133 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 0debc105b072a37e2a8ae4098a9634d841191d0a Original-Change-Id: Icf69835dc6a385a59d30092be4ac69bc80245336 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/235910 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9593 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13pistachio: increase the size of romstage to 36KIonela Voinescu
This is necessary for the subsequent changes that will add to the size of romstage. BUG=chrome-os-partner:31438 TEST=coreboot builds successfully;tested on Pistachio FPGA BRANCH=none Change-Id: I132215bd44708913d878bbd8b6147bef535b52df Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 00f73f9d80a36fc43735f093365564b9d74ed7f7 Original-Change-Id: Ie858416a1c9ab63cfe85eea40a76a093cbd2c79c Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233871 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9589 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-09pistachio: add timer frequency for SOC; correct platform IDIonela Voinescu
Corrected platform ID and added timer frequency for SOC. The timer frequency is half the CPU frequency. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: If7e03232106b52f2522fc7da586bdaf95f5eefec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d94789950d5300bbe5defbf529480d8d545e743e Original-Change-Id: I1187e4b5280eaf796777d882a2e154e2808e9e37 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241426 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9193 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-09pistachio: add SOC descriptorVadim Bendebury
With this descriptor added ramstage properly allocates memory resources and creates entries in coreboot table. This also allows to proceed to booting depthcharge, as it now can be loaded into the existing memory. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the set of patches applied the firmware properly finds depthcharge in CBFS, uncompresses it and attempts to start: ... Booting payload fallback/payload from cbfs Loading segment from rom address 0x9b000058 code (compression=1) New segment dstaddr 0x80124020 memsize 0x2099a0 srcaddr 0x9b000090 filesize 0xbbe Loading segment from rom address 0x9b000074 Entry Point 0x80124038 Loading Segment: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe lb: [0x0000000080000000, 0x0000000080013858) Post relocation: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe using LZMA [ 0x80124020, 8012596c, 0x8032d9c0) <- 9b000090 Clearing Segment: addr: 0x000000008012596c memsz: 0x0000000000208054 dest 80124020, end 8032d9c0, bouncebuffer 8ffd4f50 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 129 run 34579421 exit 129 Jumping to boot code at 80124038 ERROR: dropped a timestamp entry CPU0: stack: 9a00c800 - 9a00d800, lowest used address 9a00d498, stack used: 872 bytes entry = 80124038 Change-Id: I15809e146407d66b04f2a97c47c961fdccb8e175 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a1577c5532a064426a3ea88b6f7f30ccdae24eaf Original-Change-Id: Ifed5550f2c18430e9ae06ad1ecacaa13191b5995 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232571 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9192 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-09pistachio: modify memory layoutVadim Bendebury
With the code now running on the FPGA board it makes sense to correct the memory layout definitions to match the actual hardware. Note that the latest FPGA board firmware introduced support of the additional 128KB of SRAM (called GRAM) at base address of 0x9a000000. These are still interim values, which will be tweaked when the actual bring up board is available. BRANCH=none BUG=chrome-os-partner:31438 TEST=the code put into SPI NOR flash boots all the way to ramstage. Change-Id: I00aa5bc3aabba50df2187bb208cf2fcd11b26b3d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a6378be5cd304744b40c57a34d7a276233d45779 Original-Change-Id: I50183c2d5f9017801d5c8a7a7addf08efa492b35 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229203 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9337 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-09pistachio: set correct CBMEM top addressVadim Bendebury
This is required for proper dynamic CBMEM operation. BRANCH=none BUG=chrome-os-partner:31438 TEST=urara ramstage does not crash anymore in CBMEM initialization Change-Id: Id8e001be20fc245c91b2639f89775e594b0de966 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b7c6e4090d76a172c269bff002428015cc8aac8a Original-Change-Id: I5d44907443724891c8cff805208a7a3bb8e36752 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232292 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9191 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-09pistachio: allow more room for bootblockVadim Bendebury
32K is a more appropriate room for Pistachio bootblock. BRANCH=none BUG=chrome-os-partner:31438 TEST=there is no bootblock overflow even when compiled with -O0. Change-Id: I454746ce0b9daabc93ccbf3316655fac836af8ff Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 56adf22ba12f5a7c69d11c0c720996de32ca9149 Original-Change-Id: I74b6674aea95b1138e2168527239e2cfb4a7ad42 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232291 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9190 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-09pistachio: implement timer supportVadim Bendebury
C0_COUNT register is a free running counter clocked by the CPU frequency divided by two. On the FPGA board it results in 25 MHz, on real SOCs it will have to be figured out later. Some magic addresses and numbers are used to find out if the code is running on the FPGA board. timestamp_get() and timer_monotonic_get() are kept in the same file. The CPU initialization makes sure that CO COUNT is in fact enabled and starts from zero. BRANCH=none BUG=chrome-os-partner:33595,chrome-os-partner:31438 TEST=with timer enabled, the startup code properly initializes UART and prints the coreboot bootblock banner message on the serial console. Change-Id: I98fe330b961f677448b222917ab7d586494ed4b7 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a7324221c1d856ac72fa2b0ab586b5ea8cab3a05 Original-Change-Id: I2d518213de939e91a35f8aea174aed76d297dd72 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227888 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9188 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-07pistachio: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns pistachio to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Urara. Change-Id: I0609b307695ba6a922384ac34dd604bffcb20692 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a577918babf26adf10baa0f56a7065f5659d285 Original-Change-Id: I3ed405a3efdeec28965538d19a22f2b5b8204f01 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224503 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-02pistachio: add gpio type definitionVadim Bendebury
This is necessary to support generic gpio interface in src/lib. This file will be later populated with more GPIO definitions. BRANCH=none BUG=chrome-os-partner:31438 TEST=none Change-Id: I3fa93f1b3b1ce99d921bbfb378b3f7ae4eb652c2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 26f564ee10a770d57cb4af0a8ab5a264aaf1a7cd Original-Change-Id: I68c9c3a28fcc747575436b502cb25b31afed8700 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226181 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9184 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02urara: Fix CBFS header definitionsVadim Bendebury
Urara CBFS header configuration is broken. CBFS header needs to be right above the bootblock, and the CBFS data - 0x100 bytes above, to allow room for proper CBFS wrapper structures. Ideally only the header offset should be specified (and even that could be derived from the bootblock size). But this is a more generic problem to be addressed with different architectures' image layout requirements in mind. BRANCH=none BUG=chrome-os-partner:31438 TEST=coreboot image passes the integrity check now (it was failing before because CBGS header was overlaying the bootblock) $ FEATURES=noclean emerge-urara coreboot $ /build/urara/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/build/util/bimgtool/bimgtool \ /build/urara/firmware/coreboot.rom.serial $ cbfstool /build/urara/firmware/coreboot.rom.serial print coreboot.rom.serial: 1024 kB, bootblocksize 9956, romsize 1048576, offset 0x4100 alignment: 64 bytes, architecture: mips Name Offset Type Size fallback/romstage 0x4100 stage 7100 fallback/ramstage 0x5d00 stage 18995 config 0xa780 raw 2452 (empty) 0xb140 null 1003096 Change-Id: Id615bdcc6261dea9f36a409bd90f1e4764353bb9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8a0115963aa7460e4c7255ab8508d7d52d67fb67 Original-Change-Id: Id200ab5421661ef39b7c7713e931c39153fdc8be Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227523 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9187 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-03-30imgtec/pistachio: Bring uart driver to modern standardsPatrick Georgi
The console interface changed in upstream, and the driver didn't reflect that yet. This wasn't obvious because the driver wasn't compiled at all. Change-Id: Id18391e62e7ebd8f5fc929838ce27bf414e364f9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9165 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-28pistachio: don't open code ramstage loadingAaron Durbin
Use the run_ramstage() function to load and run ramstage. Change-Id: I783801bf506fa2f9608eefe1cd20257292c80af5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-27soc/imgtec/pistachio: Add IMGTEC SPI controller driverIonela Voinescu
The Serial Peripheral Flash Interface (SPFI) block allows communication with various devices over the SPI bus. It uses a configurable transaction interface and it clocks the bus according to the configured command, address, gap (aka dummy) and data lengths. This controller requires the SPI_ATOMIC_SEQUENCING flag set (write and read done in the same transaction) as it cannot directly control CS and will assert/de-assert CS at the beginning/end of a transaction itself. Note that the size of any transfer cannot be greater than 64KB - 1, as this is configured in a 16-bit field. The SOC has 2 SPFI interfaces each of them providing 5 slave select lines. SPFI 0 supports single and dual modes, SPFI 1 supports single, dual and quad modes. For SPFI interface 0: - The block needs the system PLL and the following top level SPI clock registers to be set: - CR_cr_top_spi0clkinternal_CTRL[2:0] with division value - CR_MIPS_CLOCK_GATE[19]: bit cr_top_SPI0CLKOUT_MIPS set - CR_cr_top_SPI0CLKOUT_CTRL[6:0] with division value - The following MFIO configuration parameters are also required: Signal name Pad name MFIO mode spim0_d0_txd MFIO_MIPS_10 0 spim0_d1_rxd MFIO_MIPS_9 0 spim0_mclk MFIO_MIPS_8 0 spim0_cs0 MFIO_MIPS_2 1 spim0_cs1 MFIO_MIPS_1 1 spim0_cs2 MFIO_MIPS_55 1 MFIO_MIPS_28 1 spim0_cs3 MFIO_MIPS_56 1 MFIO_MIPS_29 1 spim0_cs4 MFIO_MIPS_57 1 MFIO_MIMPS_30 1 For SPFI interface 1: - The block needs the system PLL and the following top level SPI clock registers to be set: - CR_cr_top_spi1clkinternal_CTRL[2:0] with division value - CR_MIPS_CLOCK_GATE[20]: bit cr_top_SPI1CLKOUT_MIPS set - CR_cr_top_SPI1CLKOUT_CTRL[6:0] with division value - The following MFIO configuration parameters are also required: Signal name Pad name MFIO mode spim1_d0_txd MFIO_MIPS_5 0 spim1_d1_rxd MFIO_MIPS_4 0 spim1_mclk MFIO_MIPS_3 0 spim1_d2 MFIO_MIPS_6 0 spim1_d3 MFIO_MIPS_7 0 spim1_cs0 MFIO_MIPS_0 0 spim1_cs1 MFIO_MIPS_1 0 MFIO_MIPS_58 1 spim1_cs2 MFIO_MIPS_2 0 MFIO_MIPS_55 2 MFIO_MIPS_31 1 spim1_cs3 MFIO_MIPS_56 2 spim1_cs4 MFIO_MIPS_57 2 BUG=chrome-os-partner:31438, chrome-os-partner:32441 TEST=Tested as bare-metal driver on Pistachio FPGA Change-Id: I3b3e4475976e6fba58cef93b12d997ec5cb26341 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 621849942e27f7d6cf2c8ade7f2c4d18d2318b91 Original-Change-Id: Ib257eb6236bd2895281175871b4ab979660f1239 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217320 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9049 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27urara: use proper SOC nameVadim Bendebury
Danube has become Pistachio, let's rename all instances where this SOC is mentioned. BUG=none TEST=board urara still builds Change-Id: Iea91419121eb6ab5665c2f9f95e82f461905268e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58696cc7c77a70dca2bfd512d695d143e1097a78 Original-Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220401 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-on: http://review.coreboot.org/9048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>