coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-10-10	soc/cavium: dynamic UART initialization for cavium cn8100	Jens Drenhaus
2018-09-30	soc/cavium/cn81xx/spi: Add function to return SPI clock	Patrick Rudolph
2018-09-18	soc/cavium/cn81xx: Don't use device_t in ramstage	Elyes HAOUAS
2018-08-24	soc/cn81xx: Add vboot support	Philipp Deppenwiese
2018-08-24	soc/cavium/cn81xx: Don't directly manipulate devicetree data	Patrick Rudolph
2018-08-24	device_tree/fit: Constify data structures	Patrick Rudolph
2018-08-10	soc/cavium/cn81xx: Fix minor things	Patrick Rudolph
2018-08-10	[HACK]cavium/cn81xx/soc: Don't advertise CAR area as usable	Patrick Rudolph
2018-08-10	arm64: Remove set_cntfrq() function	Julius Werner
2018-07-30	soc/cavium/cn81xx: Use ATF from blobs repo	Patrick Rudolph
2018-07-30	soc/cavium/bootblock: Get rid of register X1	Patrick Rudolph
2018-07-23	soc/cavium: Enable DRAM test	Patrick Rudolph
2018-07-23	soc/cavium: Apply additional devicetree fixups	Patrick Rudolph
2018-07-19	soc/cavium: Add PCI support	Patrick Rudolph
2018-07-17	bdk: Use Kconfig options instead of getenv()	Patrick Rudolph
2018-07-16	soc/cavium: Fix overflow before widen	Patrick Rudolph
2018-07-12	Coverity: Fix CID1393976	Patrick Rudolph
2018-07-10	soc/cavium: Add secondary CPU support	Patrick Rudolph
2018-07-10	soc/cavium/cn81xx: Set cntfrq_el0	Patrick Rudolph
2018-07-10	soc/cavium: Clean uart code	Patrick Rudolph
2018-07-10	soc/cavium: Enable MMU	Patrick Rudolph
2018-07-10	cavium: Add CN81xx SoC and eval board support	David Hendricks